Method for manufacturing fully self-aligned high-density 3D multi-layer memory

A method for manufacturing a fully self-aligned high-density three-dimensional (3D) multi-layer memory, comprising:

• step 1:
• forming a base structure, wherein a predetermined number of conductive medium layers and a predetermined number of insulating medium layers are disposed in such a manner that the conductive medium layers and the insulating medium layers are alternately stacked on each other, to form the base structure;
• and
• step 2:
• grooving the base structure, wherein the base structure is grooved to form a curved division groove penetrating from a top layer to a bottom layer in the base structure, so that the division groove divides the base structure into two interdigitated structures that are staggered and separated from each other;
• step 3:
• filling an insulating medium in the division groove;
• step 4:
• deep-hole etching the insulating medium in step 3 to form memory cell holes discretely arranged along the division groove, wherein the insulating medium is present between adjacent memory cell holes, and the conductive medium layers and the insulating medium layers of the base structure are exposed at the inner walls of the memory cell holes;
• and
• step 5:
• disposing various layers of medium required by a preset memory structure layer by layer onto inner walls of the memory cell holes, comprising:
• step 5.1:
• depositing an intermediate medium layer on an inner wall of each memory cell hole;
• step 5.2:
• etching the intermediate medium layer in a bottom area of the memory cell hole, to form a through hole penetrating through the intermediate medium layer;
• and
• step 5.3:
• disposing a core medium layer in each memory cell hole;
• wherein
• the conductive medium layer is a conductor, the intermediate medium layer is a memory medium, and the core medium layer is the conductor.

A method for manufacturing a fully self-aligned high-density three-dimensional (3D) multi-layer memory, comprising:

• step 1:
• forming a base structure, wherein a predetermined number of conductive medium layers and a predetermined number of insulating medium layers are disposed in such a manner that the conductive medium layers and the insulating medium layers are alternately stacked on each other, to form the base structure;
• and
• step 2:
• grooving the base structure, wherein the base structure is grooved to form a curved division groove penetrating from a top layer to a bottom layer in the base structure, so that the division groove divides the base structure into two interdigitated structures that are staggered and separated from each other;
• step 3:
• filling an insulating medium in the division groove;
• step 4:
• deep-hole etching the insulating medium in step 3 to form memory cell holes discretely arranged along the division groove, wherein the insulating medium is present between adjacent memory cell holes, and the conductive medium layers and the insulating medium layers of the base structure are exposed at the inner walls of the memory cell holes;
• and
• step 5:
• disposing various layers of medium required by a preset memory structure layer by layer onto inner walls of the memory cell holes, comprising:
• step 5.1:
• depositing an insulating layer on an inner wall of each memory cell hole, and then depositing a buffer layer on an inner wall of the insulating layer;
• step 5.2:
• etching the insulating layer and the buffer layer in a bottom area of the memory cell hole, to form a through hole penetrating through the insulating layer and the buffer layer;
• and
• step 5.3:
• disposing a core medium layer in the memory cell hole;
• wherein
• materials of the conductive medium layer, the buffer layer, and the core medium layer are one of the following:
• (1) the conductive medium layer is a P+-type semiconductor, the buffer layer is a lightly-doped N-type semiconductor, and the core medium layer is an N+-type semiconductor or a conductor;
• (2) the conductive medium layer is the N+-type semiconductor or the conductor, the buffer layer is a lightly-doped P-type semiconductor, and the core medium layer is the P+-type semiconductor;
• (3) the conductive medium layer is P-type Schottky metal, the buffer layer is the lightly-doped N-type semiconductor, and the core medium layer is the N+-type semiconductor or the conductor;
• and
• (4) the conductive medium layer is N-type Schottky metal, the buffer layer is the lightly-doped P-type semiconductor, and the core medium layer is the P+-type semiconductor or the conductor.