Method for making self-aligned source/drain mask ROM memory cell using trench etched channel

A method of manufacture of a semiconductor memory device including a silicon semiconductor substrate with a vertical channel comprising the sequence of steps as follows:

• forming a first dielectric masking layer patterned with pattern of trench openings therethrough on said substrate,
• etching of trenches in the surface of the semiconductor substrate through said first dielectric masking layer,
• said trenches having bases and sidewalls, said substrate having upper surfaces between and/or aside from said trenches,
• removing said masking layer,
• forming a spacer layer on the surface of said device,
• shaping said spacer layer to form spacers ever said silicon substrate in said trenches along said sidewalls,
• depositing a layer of a metal selected from the group consisting of W, Ti, Co, Me, and Ta ever said substrate including said trenches,
• annealing said device to form silicides between said layer of metal and said silicon substrate,
• etching away unreacted metal,
• ion implanting source/drain dopant into said substrate,
• annealing said device to activate said source/drain dopant to form source/drain regions in said silicon semiconductor substrate,
• removing said spacers from said device,
• formation of a gate oxide layer over said device, and
• forming and patterning a conductive word-line ever said dielectric layer.

A method of manufacture of a semiconductor memory device on a silicon semiconductor substrate with a vertical channel comprising the sequence of steps as follows:

• forming a silicon dioxide masking layer patterned with pattern of trench openings therethrough on said substrate,
• etching of trenches in the surface of the semiconductor substrate through said silicon dioxide masking layer,
• said trenches having bases and sidewalls, said substrate having upper surfaces between and/or aside from said trenches,
• removing said masking layer,
• forming a sub-spacer dielectric layer composed of silicon dioxide on the surface of said device,
• forming a spacer layer composed of a material selected from the group consisting of polysilicon and silicon nitride over said sub-spacer dielectric layer,
• shaping said spacer layer to form spacers in said trenches along said sidewalls,
• ion implanting source/drain ions to deposit dopant in said substrate,
• removing said spacers and said sub-spacer layer from said device,
• forming a gate oxide layer over said device,
• annealing said device to form source/drain regions in said silicon semiconductor substrate, and
• forming and patterning a conductive word-line over said dielectric layer.