G11C 7/22
Read-write [r-w] timing or clocking circuits
Official title: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
G11C7/22 (Read-write [r-w] timing or clocking circuits) appears on 9,130 US grants and 8,051 published applications in this corpus.
Search patents in G11C- Granted patents
- 9,130
- Published applications
- 8,051
- Assignees
- 781
- Inventors
- 8,424
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 2 | 0 |
| 1982 | 1 | 0 |
| 1983 | 2 | 0 |
| 1984 | 6 | 0 |
| 1985 | 7 | 0 |
| 1986 | 15 | 0 |
| 1987 | 21 | 0 |
| 1988 | 28 | 0 |
| 1989 | 36 | 0 |
| 1990 | 20 | 0 |
| 1991 | 30 | 0 |
| 1992 | 21 | 0 |
| 1993 | 29 | 0 |
| 1994 | 50 | 0 |
| 1995 | 49 | 0 |
| 1996 | 60 | 0 |
| 1997 | 101 | 0 |
| 1998 | 116 | 0 |
| 1999 | 188 | 0 |
| 2000 | 227 | 0 |
| 2001 | 222 | 95 |
| 2002 | 225 | 239 |
| 2003 | 206 | 240 |
| 2004 | 225 | 227 |
| 2005 | 209 | 242 |
| 2006 | 230 | 284 |
| 2007 | 240 | 295 |
| 2008 | 251 | 289 |
| 2009 | 236 | 263 |
| 2010 | 275 | 296 |
| 2011 | 283 | 222 |
| 2012 | 250 | 257 |
| 2013 | 265 | 285 |
| 2014 | 352 | 338 |
| 2015 | 344 | 325 |
| 2016 | 405 | 274 |
| 2017 | 385 | 337 |
| 2018 | 362 | 361 |
| 2019 | 458 | 492 |
| 2020 | 494 | 418 |
| 2021 | 461 | 436 |
| 2022 | 398 | 437 |
| 2023 | 402 | 480 |
| 2024 | 399 | 362 |
| 2025 | 350 | 295 |
| 2026 | 190 | 262 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Automatic adaptive signaling over a pin of an integrated circuit device6 Oct 2026US 12,755,767 B2Micron Technology, Inc.
- Memory device that includes a duty correction circuit, memory controller that includes a duty sensing circuit, and storage device that includes a memory device6 Oct 2026US 12,755,768 B2Samsung Electronics Co., Ltd.
- Methods and apparatus including sampler circuitry for performing offest calibration6 Oct 2026US 12,755,769 B2Samsung Electronics Co., Ltd.
- Memory readout circuit29 Sep 2026US 12,749,515 B2Infineon Technologies AG
- Method and device for adjusting phase of bidirectional data strobe (DQS) signal29 Sep 2026US 12,749,516 B2Shenzhen Pango Microsystems Co., Ltd
- Memory performing training operation, memory system, and operation method of the memory system8 Oct 2026US 2026/0310468 A1SK hynix Inc.
- Bit line sense amplifier and a memory apparatus using the same8 Oct 2026US 2026/0311732 A1SK hynix Inc.
- Memory system, memory controller, and method of operating memory controller with training circuit8 Oct 2026US 2026/0311788 A1Samsung Electronics Co., Ltd.
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Memory device and operating method of the same1 Oct 2026US 2026/0301783 A1SK hynix Inc.
Most cited
By later US patents
- Output enable signal generation circuit of semiconductor memory1,017US 8,400,851 B2SK hynix Inc. · 2013
- Apparatus for synchronously generating clock signals in a data processing system430US 5,243,703 ARambus Inc. · 1993
- Method and apparatus for accessing a memory device430US 6,157,578 ASTMicroelectronics S.r. l. · 2000
- Apparatuses and methods for performing logical operations using sensing circuitry426US 8,971,124 B1Micron Technology, Inc. · 2015
- Scannable sense amplifier circuit421US 5,915,084 AAdvanced Micro Devices, Inc. · 1999