Method and apparatus for accessing a memory device

A random access memory device, comprising:

• an array of memory cells arranged in a plurality of rows and columns of memory cells, including a plurality of word lines with memory cells in each row of memory cells being connected to a distinct word line and a plurality of bit lines with memory cells in each column of memory cells being connected to a distinct bit line;
• a plurality of sense amplifiers, each sense amplifier being coupled to a distinct pair of bit lines and selectively enabled, during a memory read operation, to sense a charge differential appearing across a corresponding pair of bit lines and drive the corresponding pair of bit lines towards reference voltage levels based upon a Polarity of the charge differential;
• a plurality of latch elements, each latch element being capable of storing data, coupled to a distinct pair of bit lines and selectively disconnected from at least one reference voltage source;
• and
• control circuitry, operably connected to the memory cell array, the sense amplifiers and the latch elements, for transferring the data between each of the latch elements and an entire row of memory cells connected to a selected word line substantially concurrently, the control circuitry disconnects the latch elements from the at least one reference voltage source during a memory read operation until the sense amplifiers have drive the bit lines towards the reference voltage levels.

A random access memory device, comprising:

• an array of memory cells arranged in a plurality of rows and columns of memory cells, including a plurality of word lines with memory cells in each row of memory cells being connected to a distinct word line and a plurality of bit lines with memory cells in each column of memory cells being connected to a distinct bit line;
• sense amplifiers, coupled to the bit lines, for sensing charge differentials appearing across bit line pairs during a memory read operation and driving the bit lines towards high and low reference voltage supply levels based upon a polarity of the charge differentials;
• a plurality of load circuits, each load circuit being coupled to a distinct pair of bit lines and selectively disconnected from high and low reference voltage supplies each bit line pair being connected to a distinct load circuit;
• and
• control circuitry, operably connected to the memory cell array, the sense amplifiers and the load circuits, for writing data provided by the load circuits into each memory cell connected to a selected word line substantially concurrently during the memory write operation, and placing data stored in a row of memory cells into the load circuits substantially concurrently during a memory read operation, the control circuitry disconnecting the load circuits from the high and low reference voltage supplies during the memory read operation prior to the sense amplifiers driving the bit lines and connecting the load circuits to the high and low reference voltage supplies during the memory read operation after the sense amplifiers commence driving the bit lines.

A method for accessing a memory device having a plurality of memory cells arranged in a plurality of rows and columns, with each memory cell in a row being coupled to the same word line and each memory cell in a column being coupled to the same bit line, a plurality of column input/output lines, and a plurality of sense amplifiers and latches with each sense amplifier and latch being coupled to a distinct pair of bit lines, the method comprising the steps of:

• decoupling the sense amplifiers from reference voltage sources which provide power to the sense amplifiers;
• decoupling the latches from the reference voltage sources which provide power thereto;
• equalizing voltage levels appearing on nodes within the sense amplifiers;
• connecting an entire row of memory cells to the bit lines so that the charge appearing across each bit line pair corresponds to a binary data value stored in the memory cell connected thereto;
• coupling the sense amplifiers to the reference voltage sources which provide power thereto so that the sense amplifiers drive the bit lines towards reference voltage levels based upon the binary data values appearing on the bit lines;
• disconnecting the row of memory cells from the bit lines;
• connecting a bit line from each bit line pair to a distinct column I/O line so that a voltage level appearing on each column I/O line represents the binary data value appearing on the bit line pair connected thereto;
• connecting each latch to a distinct column I/O line;
• and
• coupling the latches to the reference voltage sources which provide power thereto so that the latches drive the column I/O lines towards reference voltage levels based upon the voltage level appearing on the column I/O lines;
• and
• accessing the latched data bit values in a sequential manner.