Apparatuses and methods for performing logical operations using sensing circuitry

A method for performing a logical operation, comprising:

• sensing, via a sense amplifier coupled to a sense line, a data value stored in a memory cell, the data value serving as a first input of the logical operation;
• transferring the determined data value into a latch of a compute component coupled to the sense amplifier via enabling a first pass transistor coupled to the sense line and a second pass transistor coupled to a complementary sense line;
• sensing, via the sense amplifier, a number of data values stored in a number of different memory cells coupled to the sense line, the number of data values serving as a respective number of additional inputs of the logical operation;
• determining a result of the logical operation using the compute component without performing a sense line address access.

An apparatus, comprising:

• an array of memory cells;
• and
• sensing circuitry coupled to the array and configured to:
• determine data values stored in a first number of memory cells coupled to a first access line of the array, each of the first number of memory cells coupled to a respective sense line of a number of sense lines;
• and
• perform, in parallel, logical operations using the data values stored in the first number of memory cells as a number of first inputs and data values stored in a second number of memory cells coupled to a second access line of the array as a number of second inputs, wherein each of the second number of memory cells are coupled to a respective sense line of the number of sense lines;
• and
• wherein the logical operations are performed in parallel without transferring data via an input/output line of the array.

A method for performing a logical operation, comprising:

• performing a first operation phase by:
• activating a first access line of an array of memory cells coupled to sensing circuitry comprising:
• a sense amplifier coupled to a sense line and including a primary latch;
• and
• a compute component including secondary latch;
• activating the sense amplifier such that a data value corresponding to a first input of the logical operation is transferred from a memory cell coupled to the first access line and to the sense line to the primary latch;
• enabling a pair of pass transistors coupled to the sense amplifier and to the secondary latch;
• activating the secondary latch while the pair of transistors remain enabled such that the data value corresponding to the first input is transferred to the secondary latch;
• and
• deactivating the first access line and the sense amplifier and disabling the pair of pass transistors;
• performing a second operation phase by:
• activating a second access line of the array:
• activating the sense amplifier such that a data value corresponding to a second input of the logical operation is transferred from a memory cell coupled to the second access line and to the sense line to the primary latch;
• enabling, based on a particular logical operation being performed, only one of the pair of pass transistors, wherein the secondary latch remains activated during the second operation phase;
• deactivating the second access line and the sense amplifier and disabling the one of the pair of pass transistors, wherein after the second operation phase the secondary latch stores either a data value corresponding to a result of the logical operation or a data value corresponding to an inverse of the result of the logical operation;
• and
• performing a last operation phase by transferring the result of the logical operation from the compute component to at least one of:
• the array;
• the sense amplifier;
• and
• an external location.

A method for performing a logical operation, comprising:

• determining a data value serving as a first input of the logical operation via a sense amplifier coupled to a sense line of the array without activating an access line of the array;
• providing the determined data value to a latch of a compute component coupled to the sense amplifier without activating an input/output (I/O) line coupled to the sense amplifier;
• sensing, via the sense amplifier, a number of data values stored in a number of memory cells coupled to the sense line, the number of data values serving as a respective number of additional inputs of the logical operation;
• determining a result of the logical operation using the compute component without performing a sense line address access.

An apparatus, comprising:

• an array of memory cells;
• and
• sensing circuitry comprising a number of sense amplifier/compute component pairs coupled to a respective number of sense lines of the array, the sensing circuitry configured to:
• determine at least one input of a logical operation without activating an access line of the array;
• determine a number of additional inputs of the logical operation by sensing a respective number of memory cells coupled to a particular sense line;
• and
• perform an accumulate operation on the at least one input and the number of additional inputs using a latch of a compute component coupled to the particular sense line and without performing a sense line address access.