Memory device that includes a duty correction circuit, memory controller that includes a duty sensing circuit, and storage device that includes a memory device

A controller comprising:

• a clock pin;
• a plurality of input/output pins commonly connected to a plurality of memories;
• and
• a plurality of duty sensing circuits, wherein each duty sensing circuit of the plurality of duty sensing circuits respectively corresponds to a memory of the plurality of memories,
• wherein the controller is configured to:
• transmit a chip enable command through the plurality of input/output pins to the plurality of memories in a first period of a chip enable period;
• transmit an address for the plurality of memories through the plurality of input/output pins to the plurality of memories in a second period of the chip enable period;
• transmit a DCC command through the plurality of input/output pins to the plurality of memories in a first period of a DCC training period;
• transmit the address for the plurality of memories through the plurality of input/output pins to the plurality of memories in a second period of the DCC training period;
• and
• transmit a clock signal through the clock pin to the plurality of memories in a third period of the DCC training period, and
• wherein the plurality of duty sensing circuits is configured to perform duty sensing operations on signals received from the plurality of memories in parallel during the third period of the DCC training period.

A memory device comprising:

• a clock pin;
• a plurality of memories connected to the clock pin;
• and
• a plurality of input/output pins commonly connected to the plurality of memories,
• wherein the memory device is configured to:
• receive a chip enable command through the plurality of input/output pins in a first period of a chip enable period;
• receive an address through the plurality of input/output pins in a second period of the chip enable period;
• receive a duty correction circuit (DCC) command through the plurality of input/output pins in a first period of a DCC training period;
• receive the address through the plurality of input/output pins in a second period of the DCC training period;
• and
• receive a clock signal through the clock pin in a third period of the DCC training period,
• wherein, in response to the address indicating the plurality of memories, the plurality of memories is configured to perform duty correction operations on a plurality of internal clock signals generated based on the clock signal during the third period of the DCC training period, and
• wherein, in response to the address indicating a memory of the plurality of memories, the memory is configured to perform a duty correction operation on an internal clock signal generated based on the clock signal during the third period of the DCC training period.