G11C 7/227
Timing of memory operations based on dummy memory elements or replica circuits
Official title: {Timing of memory operations based on dummy memory elements or replica circuits}
G11C7/227 (Timing of memory operations based on dummy memory elements or replica circuits) appears on 437 US grants and 440 published applications in this corpus.
Search patents in G11C- Granted patents
- 437
- Published applications
- 440
- Assignees
- 119
- Inventors
- 706
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1997 | 1 | 0 |
| 1998 | 0 | 0 |
| 1999 | 1 | 0 |
| 2000 | 1 | 0 |
| 2001 | 2 | 1 |
| 2002 | 10 | 10 |
| 2003 | 7 | 8 |
| 2004 | 7 | 3 |
| 2005 | 7 | 10 |
| 2006 | 7 | 8 |
| 2007 | 11 | 9 |
| 2008 | 6 | 17 |
| 2009 | 8 | 14 |
| 2010 | 20 | 11 |
| 2011 | 12 | 13 |
| 2012 | 14 | 17 |
| 2013 | 12 | 28 |
| 2014 | 23 | 29 |
| 2015 | 36 | 29 |
| 2016 | 27 | 18 |
| 2017 | 34 | 17 |
| 2018 | 32 | 29 |
| 2019 | 25 | 27 |
| 2020 | 21 | 18 |
| 2021 | 21 | 18 |
| 2022 | 22 | 24 |
| 2023 | 14 | 27 |
| 2024 | 18 | 22 |
| 2025 | 23 | 22 |
| 2026 | 15 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Apparatuses, systems, and methods for data timing alignment with fast alignment mode22 Sep 2026US 12,744,074 B2Micron Technology, Inc.
- Adjustable delay propagation of a control signal to different page buffer driver groups4 Aug 2026US 12,700,439 B2Micron Technology, Inc.
- Offset cancellation4 Aug 2026US 12,700,440 B2
- Memory device having tracking word line with adjust circuit, method of operating same and method of manufacturing same2 Jun 2026US 12,646,543 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Memory device with soft programmed dummy cells and method of operating the same19 May 2026US 12,633,347 B2SK hynix Inc.
- Semiconductor apparatus adjusting a phase skew between a clock signal and data24 Sep 2026US 2026/0290417 A1SK hynix Inc.
- Memory devices with selective tracking scheme and methods for operating the same13 Aug 2026US 2026/0237430 A1
- Semiconductor integrated circuit and data transfer method2 Jul 2026US 2026/0188360 A1Nuvoton Technology Corporation Japan
- Memory device including pulse generator2 Jul 2026US 2026/0188383 A1Samsung Electronics Co., Ltd.
- System with Memory Device Replica for Stable Read Operations25 Jun 2026US 2026/0179665 A1
Most cited
By later US patents
- Semiconductor memory device capable of generating internal data read timing precisely212US 6,760,269 B2Renesas Technology Corp. · 2004
- Multiple bitcells tracking scheme semiconductor memory array173US 8,760,948 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Location based timing scheme in memory design141US 6,434,736 B1Intel Corporation · 2002
- Method and apparatus for a low power self-timed memory control system70US 5,596,539 ALSI Logic Corporation · 1997
- Tracking mechanism for writing to a memory cell67US 8,964,492 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015