Method and apparatus for a low power self-timed memory control system

A memory system, comprising:

• a word line decoder receiving a word line enable signal and an address and including a plurality of drivers for asserting one of a plurality of corresponding word line select signals on one of a corresponding plurality of select lines, said word line decoder for decoding said address and for activating a corresponding one of said plurality of drivers in response to the assertion of said word line enable signal, said word line decoder including a dummy driver for asserting a dummy select signal on a dummy select line in response to each assertion of said word line enable signal;
• a memory array, comprising:
• a core memory including a matrix of core memory cells organized in rows and columns, each core memory cell of each row coupled to and corresponding with one of said plurality of select lines, each core memory cell of each column coupled to a corresponding pair of complementary bit lines for asserting output data;
• and
• a dummy row and dummy column of memory cells located on two adjacent outer edges of said core memory for mirroring said rows and columns of said core memory cells, wherein each memory cell of said dummy row is coupled to load said dummy select line and wherein each memory cell of said dummy column is coupled to load a pair of complementary dummy bit lines, said dummy row and dummy column further including a fixed memory cell coupled to said dummy select line for receiving said dummy select signal and for respondingly asserting a predetermined logic level on said pair of complementary dummy bit lines;
• corresponding pair of complementary bit lines, each being enabled by a sense enable signal for sensing and asserting a corresponding output data bit of said output data when enabled, but otherwise being disabled;
• an array of latches receiving a latch signal for latching said sensed output data;
• a dummy sense amplifier coupled to said pair of complementary dummy bit line signals for sensing said predetermined logic signal and for respondingly asserting a timing signal, said dummy sense amplifier biased relative to said core sense amplifiers in favor of an opposite logic level as said predetermined logic level;
• and
• control logic coupled to said array of latches, said dummy sense amplifier and said word line decoder and receiving a clock signal, said control logic for deasserting said sense enable signal to disable said array of core sense amplifiers while said clock signal is deasserted, for asserting said word line enable signal and said sense enable signal in response the assertion of said clock signal, and for deasserting said word line enable signal and said sense enable signal and for asserting said latch signal in response to the assertion of said timing signal.

A self-timed memory control system for accessing data in a memory system in response to the assertion of a clock signal, the memory system including a core memory array with rows and columns of core memory cells, a corresponding array of word line decoders for asserting corresponding word line select signals for selecting a row of memory cells, a corresponding array of sense amplifiers receiving a sense enable signal for enabling the sense amplifiers to sense output data in the core memory cells and for disabling the sense amplifiers, and a corresponding array of latches for latching the sensed output data, said control system comprising:

• control logic for asserting a word line enable signal and the sense enable signal in response to the assertion of the clock signal, and for deasserting the sense enable signal and asserting a latch signal to latch the sensed output data in response to subsequent assertion of a timing signal;
• a dummy column of fixed memory cells located along an adjacent outer edge of the core memory array opposite the word line drivers for mirroring the columns of the core memory cells, wherein each memory cell of said dummy column is coupled to load a pair of complementary dummy bit lines, and wherein each said dummy memory cell receives corresponding word line select signals for respondingly asserting a predetermined logic level on said pair of complementary dummy bit lines;
• and
• a dummy sense amplifier coupled to said pair of complementary dummy bit lines at an opposite end of said dummy column as said fixed dummy memory cell for sensing said predetermined logic level and for respondingly asserting said timing signal, said dummy sense amplifier being biased to favor an opposite logic level of said predetermined logic level for adding timing margin.

A method for controlling a memory device in response to assertion of a clock signal for low power consumption, the memory device including a core memory array and a corresponding array of sense amplifiers, comprising the steps of:

• providing a dummy path of memory cells adjacent the core memory array forming a worst case timing path corresponding to the size of the core memory array;
• activating the array of sense amplifiers in response to a memory access;
• the dummy path of memory cells asserting a predetermined logic level on a pair of complementary dummy bit lines in response to a memory access;
• providing a dummy sense amplifier for detecting the predetermined logic level and for asserting a timing signal, and further biasing the dummy sense amplifier to favor an opposite logic level as the predetermined logic level for adding timing margin;
• providing an inverter having an input for detecting the timing signal and an output for asserting an inverted timing signal, and further biasing the input of the inverter to favor the opposite logic level for adding timing margin;
• latching the output data of the core memory array in response to the inverted timing signal being asserted;
• and
• turning off the array of sense amplifiers when the output data is latched.