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US 6,434,736 B1Granted
Location based timing scheme in memory design
AssigneeIntel Corporation
InventorsMark A. Schaecher, Richard J. Burgess, Jr., Jay B. Miller
Life of this patent
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Abstract
A method and apparatus for improving the access time of a memory device is described. The location based timing scheme utilizes a subset of the address bits to adjust the timing of the sense amplifier enable in order to achieve a faster read of the information stored in the memory cell.
Claims30
A method for controlling a sense amplifier enable signal during a read operation in a memory array, the method comprising:
- selecting a subset of address bits from an address of a memory cell to be read, wherein the subset of address bits represents one of a plurality of regions in the memory array, and wherein each region of said plurality of regions comprises a plurality of memory cells, and is associated with a distinct region access time requirement;
- determining the one of said plurality of regions based on said subset of address bits;
- selecting the memory cell to be read from the plurality of memory cells;
- and
- timing the sense amplifier enable signal for the memory cell to be read by:
- creating a distinct time delay for each region based on each region access time requirement;
- and
- asserting the sense amplifier enable signal for the memory cell to be read after the corresponding time delay is satisfied.
5 more elements
A memory for use in a computer system, the memory comprising:
- a memory array divided in a plurality of regions, wherein each region of the plurality of regions comprises a plurality of memory cells, and is associated with a distinct region access time requirement;
- and
- an address location timing circuit to generate a sense amplifier enable signal by:
- creating a distinct time delay for each region based on each region access time requirement;
- and
- asserting the sense amplifier enable signal for a memory cell to be read after the time delay for the region containing the memory cell to be read has been satisfied.
3 more elements
A computer system comprising:
- a main memory;
- and
- a processor coupled to the main memory, wherein said processor includes an on-chip cache memory comprising:
- a memory array divided in a plurality of regions, wherein each region of the plurality of regions comprises a plurality of memory cells, and is associated with a distinct region access time requirement;
- and
- an address location timing circuit for controlling a sense amplifier enable signal during a memory read operation, wherein said address location timing circuit generates a sense amplifier enable signal by:
- creating a distinct time delay for each region based on each region access time requirement;
- and
- asserting the sense amplifier enable signal for a memory cell to be read after the time delay for the region containing the memory cell to be read has been satisfied.
6 more elements
A computer system comprising:
- a processor;
- a main memory coupled to the processor;
- and
- a cache memory coupled to the processor and the main memory, wherein said cache memory comprises:
- a memory array divided in a plurality of regions, wherein each region of the plurality of regions comprises a plurality of memory cells, and is associated with a distinct region access time requirement;
- and
- an address location timing circuit for controlling a sense amplifier enable signal during a memory read operation, wherein said address location timing circuit generates a sense amplifier enable signal by:
- creating a distinct time delay for each region based on each region access time requirement;
- and
- asserting the sense amplifier enable signal for a memory cell to be read after the time delay for the region containing the memory cell to be read has been satisfied.
7 more elements
A method comprising:
- receiving an address of a memory cell to be read from a memory array, the memory array having a plurality of regions each associated with a distinct access time requirement;
- identifying a region of the plurality of regions in which the memory cell resides based upon a portion of the address;
- and
- creating a distinct time delay for each region based on each region access time requirement;
- and
- reading the memory cell by enabling sense amplifiers coupled to the memory array by asserting the sense amplifier enable signal for the memory cell to be read after the corresponding time delay is satisfied.
3 more elements
A method comprising:
- receiving a physical address of a memory cell to be read from a memory array;
- and
- adjusting the sensing of the memory cell by:
- creating a distinct time delay for each of a plurality of regions of the memory array based on distinct access time requirements associated with the plurality of regions;
- and
- enabling sense amplifiers coupled to the memory array after the time delay for the region containing the memory cell has been satisfied.
3 more elements
A memory comprising:
- a memory array having a plurality of regions each comprising a plurality of memory cells, and each being associated with a distinct access time requirement;
- an address location timing circuit capable of generating a sense amplifier enable signal by:
- creating a distinct time delay for each of a plurality of regions of the memory array based on distinct access time requirements associated with the plurality of regions;
- and
- enabling sense amplifiers coupled to the memory array for a memory cell to be read after the time delay for the region containing the memory cell has been satisfied;
- decoding circuitry coupled to the memory array to generate wordline and bitline signals;
- and
- a plurality of sense amplifiers coupled to the memory array and responsive to the sense amplifier enable signal.
5 more elements
Dependencies are inferred from the claim text.