Semiconductor memory device capable of generating internal data read timing precisely

A semiconductor memory device comprising:

• a plurality of normal cells arranged in rows and columns;
• a plurality of dummy cells arranged, in at least one column, sharing the rows with the normal cells and divided into a plurality of blocks in a column extending direction;
• a plurality of normal bit lines, arranged corresponding to the columns of the normal cells, each having normal cells on a corresponding column connected;
• a plurality of divided dummy bit lines, arranged corresponding to the blocks of the column of said dummy cells, each having dummy cells in a corresponding block connected;
• a sense amplifier for sensing and amplifying data in a selected cell of the normal cells;
• and
• a sense control circuit responsive to a potential change on either of said plurality of divided dummy bit lines, for activating said sense amplifier.