Memory device having tracking word line with adjust circuit, method of operating same and method of manufacturing same

A method of operating a memory device, the method comprising:

• raising a first voltage on a first word line towards a first reference voltage, the first word line being coupled to a first array of memory cells, and further being coupled to ones of the memory cells in a corresponding one of rows of the first array;
• and
• raising a second voltage on a second word line towards the first reference voltage, the second word line being coupled to a second array of tracking cells, the second array being configured to emulate the first array;
• hindering the first voltage on the first word line from substantially reaching the first reference voltage;
• and
• hindering the second voltage on the second word line from substantially reaching the first reference voltage.

A method of forming a memory device, the method comprising:

• forming active regions in a substrate;
• forming source/drain (S/D) regions in the active regions as first transistor-components, wherein areas of the active regions between corresponding S/D regions are channel regions representing second transistor-components;
• forming gate structures over corresponding ones of the channel regions as third transistor-components;
• forming metal-to-S/D (MD) contact structures over corresponding ones of the S/D regions as fourth transistor-components;
• forming via-to-gate/MD (VGD) structures over corresponding ones of the gate structures and the MD contact structures as fifth transistor-components;
• relative to an orthographic projection of the memory device onto a reference plane, the memory device being arranged into nonoverlapping areas including a bit cells area, a main input/output (I/O) area, a main controller area, and a word line driver area;
• the VGD structures electrically coupling corresponding sets of the first to fourth transistor-components including:
• a first set as a first array of memory cells in the bit cells area;
• a second set as a second array of tracking cells in the bit cells area and being configured to emulate the first array;
• a third set as a first adjust circuit in one of the nonoverlapping areas other than the bit cells area;
• and
• a fourth set as an adjust-timing circuit in the main controller area and being coupled to the first adjust circuit;
• and
• forming metallization segments in corresponding metallization layers and interconnection structures in corresponding interconnection layers on an interleaved layer basis correspondingly over the first to fourth sets;
• and
• wherein:
• the forming metallization segments and interconnection structures produces:
• a first word line in the bit cells area and coupled to ones of the memory cells in a corresponding one of rows of the first array and to the tracking cells;
• and
• a second word line in the main I/O area configured to emulate the first word line;
• and
• the forming metallization segments and interconnection structures electrically couples:
• the first adjust circuit to the second word line;
• and
• the adjust-timing circuit to the first adjust circuit.