Memory devices with selective tracking scheme and methods for operating the same

A circuit, comprising:

• a controller configured to generate a tracking word line signal present on a tracking word line coupled to one or more tracking memory cells, based on a clock pulse signal;
• and
• a comparator configured to determine a mode selection signal being equal to (i) a first logic state in response to identifying that a varying supply voltage is equal to or lower than a reference voltage;
• or (ii) a second logic state in response to identifying that the varying supply voltage is higher than the reference voltage;
• wherein the controller is further configured to:
• reset the tracking word line signal through the one or more tracking memory cells and a combination of logic gates of the controller, when the mode selection signal is determined at the first logic state;
• and
• reset the tracking word line signal through a portion of the combination of logic gates, when the mode selection signal is determined at the second logic state.

A method, comprising:

• comparing a voltage level of a varying supply voltage with a reference voltage to determine a logic state of a mode selection signal, wherein the varying supply voltage is configured to power a memory array comprising a plurality of nominal memory cells and a tracking memory cell;
• in response to identifying the logic state being equal to a first logic state, providing a first signal on a tracking word line connected to the tracking memory cell and then providing a second signal to reset the first signal based on a third signal present on a tracking bit line connected to the tracking memory cell;
• and
• in response to identifying the logic state being equal to a second logic state, providing a fourth signal directly based on the first signal, wherein the fourth signal is configured to directly transition the second signal.