Memory readout circuit
AssigneeInfineon Technologies AG
InventorsMihail Jefremow, Thomas Kern, Arndt Voigtlander
Life of this patent
Estimating the term…
Abstract
One embodiment describes a memory readout circuit. The memory readout circuit includes a readout node having a capacitance that is discharged by the memory cell to read out a memory cell by means of a cell current, a level detector that is configured to provide a digital output signal and to switch over the output signal when the potential of the readout node (due to the discharge of the readout node) crosses a switching threshold (depending on the selection of the level and the polarity downward or upward, that is to say the switching threshold is overshot or undershot), and a control circuit that is configured to set the switching threshold and/or the switching speed of the level detector depending on the cell current.
Claims20
A memory readout circuit configured to read a data state from a memory cell, the memory readout circuit comprising:
- a readout node having a capacitance that is discharged by the memory cell to read out the data state from the memory cell by means of a cell current;
- a level detector that is set up to provide a digital output signal and to switch a state of the digital output signal when a potential of the readout node crosses a switching threshold;
- and
- a control circuit that is configured to set the switching threshold and/or a switching speed of the level detector depending on the cell current.
A memory device, comprising:
- a memory cell;
- a bitline coupled to the memory cell;
- a comparator having a first input, a second input, and an output;
- a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor being coupled to a supply voltage terminal, and the second terminal of the first transistor being coupled to the first input of the comparator;
- a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor being coupled to the second terminal of the first transistor and being coupled to the first input of the comparator, and the second terminal of the second transistor being coupled to the bitline;
- a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor being coupled to a capacitance, the capacitance being coupled to the first input of the comparator;
- and
- a fourth transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the fourth transistor being coupled to the first terminal of the third transistor and being coupled to the second terminal of the fourth transistor.
Dependencies are inferred from the claim text.