Back to results
US 2026/0301783 A1Published application
Memory device and operating method of the same
AssigneeSK hynix Inc.
InventorsHong Ki MOON, Min Su PARK
Life of this patent
Estimating the term…
Abstract
An operating method of a memory device, includes receiving a row address that designates a first word line and an active command, enabling the first word line and activating a first bit line sense amplifier (BLSA) array corresponding to the first word line, receiving a row address that designates a second word line and the active command, and enabling the second word line and activating a second BLSA array corresponding to the second word line.
Claims19
An operating method of a memory device, the operating method comprising:
- receiving a row address that designates a first word line and an active command;
- enabling the first word line and activating a first bit line sense amplifier (BLSA) array corresponding to the first word line;
- receiving a row address that designates a second word line and the active command;
- and
- enabling the second word line and activating a second BLSA array corresponding to the second word line.
2 more elements
A memory device comprising:
- a plurality of data storage regions each comprising a plurality of memory cells;
- a plurality of bit line sense amplifier (BLSA) arrays configured to sense and amplify data stored in the respective plurality of data storage regions;
- and
- a RAS control circuit configured to disable, in response to a word line precharge command, one or more enabled word lines among a plurality of word lines coupled to the plurality of data storage regions and configured to deactivate, in response to a bit line precharge command, one or more activated BLSA arrays among the plurality of BLSA arrays.
1 more element
A memory device comprising:
- a row decoder configured to enable a first word line by receiving a row address that designates the first word line and an active command and enable a second word line by receiving a row address that designates a second word line and the active command;
- and
- a RAS control circuit configured to activate a first bit line sense amplifier (BLSA) corresponding to the first word line based on the row address that designates the first word line and activate a second BLSA corresponding to the second word line based on the row address that designates the second word line.
Dependencies are inferred from the claim text.