Bit line sense amplifier and a memory apparatus using the same
AssigneeSK hynix Inc.
InventorKwang Soo KIM
Life of this patent
Estimating the term…
Abstract
A memory apparatus includes a bit line sense amplifier. The bit line sense amplifier includes an input circuit, a latch circuit, and an isolation switching circuit. The input circuit is configured to change the voltage levels of first and second nodes based on the voltage levels of a first bit line and a second bit line. The latch circuit is configured to change the voltage levels of the first and second nodes based on the voltage levels of the second and first nodes, respectively. The isolation switching circuit is configured to couple the first bit line to the second node based on a first isolation switching signal and to couple the second bit line to the first node based on a second isolation switching signal.
Claims21
A memory apparatus comprising:
- an input circuit configured to change a voltage level of a first node based on a voltage level of a first bit line and to change a voltage level of a second node based on a voltage level of a second bit line;
- a latch circuit configured to change the voltage level of the second node based on the voltage level of the first node and to change the voltage level of the first node based on the voltage level of the second node;
- an isolation switching circuit configured to couple the first bit line to the second node based on a first isolation switching signal and to couple the second bit line to the first node based on a second isolation switching signal;
- and
- an isolation switching control circuit configured to increase a voltage level of the first isolation switching signal to a voltage level of an isolation voltage and to gradually increase a voltage level of the second isolation switching signal to the voltage level of the isolation voltage, when an isolation switching enable signal is enabled.
A memory apparatus comprising:
- an input circuit configured to change a voltage level of a first node based on a voltage level of a first bit line and to change a voltage level of a second node based on a voltage level of a second bit line;
- a latch circuit configured to change the voltage level of the second node based on the voltage level of the first node and to change the voltage level of the first node based on the voltage level of the second node;
- an isolation switching circuit configured to couple the first bit line to the second node based on a first isolation switching signal and to couple the second bit line to the first node based on a second isolation switching signal;
- and
- a mismatch compensation circuit configured to couple the first bit line to the first node based on a first mismatch compensation signal and to couple the second bit line to the second node based on a second mismatch compensation signal.
Dependencies are inferred from the claim text.