US 12,755,769 B2 · Methods and apparatus including sampler circuitry for performing offest calibration

Abstract

A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

Claims20

Dependent claims

A memory system comprising:

a memory controller configured to transmit a data signal and a data clock signal in synchronization with the data signal;
and
a memory device comprising:
a clock control circuit configured to divide the data clock signal to generate a plurality of divided clock signals,
a plurality of sampler circuits configured to sample the data signal in synchronization with the plurality of divided clock signals;
a calibration circuit configured to provide a plurality of offset clock signals having an opposite phase to each other to the plurality of sampler circuits to perform offset calibration of the plurality of sampler circuits based on outputs of the plurality of sampler circuits generated in synchronization with the plurality of offset clock signals.

3 more elements

A method for operating a semiconductor memory device comprising:

applying a plurality of offset clock signals having an opposite phase to each other to a plurality of sampler circuits;
performing offset calibration of the plurality of sampler circuits based on outputs of the plurality of sampler circuits generated in synchronization with the plurality of offset clock signals;
receiving a data clock signal;
dividing the data clock signal to generate a plurality of divided clock signals;
sampling a data signal in synchronization with the plurality of divided clock signals;
and
writing the sampled data signal to a plurality of memory cells.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/794,825Filed 5 Aug 2024 · continuation

Priority

KR 10-2022-000546813 Jan 2022

Published

US 2024/0395298 A128 Nov 2024

Granted

6 Oct 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 7/06
Arrangements for writing information into, or reading information out from, a digital store: sense amplifiers; Associated circuits , e.g. timing…
G11C 7/1096
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: write circuits, e.g.…
G11C
Static stores

Family

Application17/939,016Parent of this continuation · filed 7 Sep 2022

US 2024/0395298 A1Pre-grant publication · published 28 Nov 2024

US 12,080,379 B2Parent of this continuation

US 2023/0223060 A1Published application

US 12,755,769 B2This patent

From the US filing history. Foreign family members aren’t listed.

Methods and apparatus including sampler circuitry for performing offest calibration

Life of this patent

Methods and apparatus including sampler circuitry for performing offest calibration

Life of this patent

Abstract

Claims20