G11C 7/1072
For memories with random access ports synchronised on clock signal pulse trains
Official title: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
G11C7/1072 (For memories with random access ports synchronised on clock signal pulse trains) appears on 3,066 US grants and 2,365 published applications in this corpus.
Search patents in G11C- Granted patents
- 3,066
- Published applications
- 2,365
- Assignees
- 393
- Inventors
- 2,848
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1992 | 6 | 0 |
| 1993 | 3 | 0 |
| 1994 | 4 | 0 |
| 1995 | 15 | 0 |
| 1996 | 33 | 0 |
| 1997 | 54 | 0 |
| 1998 | 103 | 0 |
| 1999 | 126 | 0 |
| 2000 | 157 | 0 |
| 2001 | 205 | 73 |
| 2002 | 178 | 172 |
| 2003 | 144 | 142 |
| 2004 | 130 | 116 |
| 2005 | 112 | 120 |
| 2006 | 100 | 93 |
| 2007 | 93 | 93 |
| 2008 | 66 | 94 |
| 2009 | 83 | 72 |
| 2010 | 67 | 67 |
| 2011 | 72 | 64 |
| 2012 | 63 | 82 |
| 2013 | 85 | 109 |
| 2014 | 105 | 137 |
| 2015 | 126 | 152 |
| 2016 | 161 | 153 |
| 2017 | 155 | 130 |
| 2018 | 139 | 143 |
| 2019 | 123 | 82 |
| 2020 | 100 | 58 |
| 2021 | 76 | 58 |
| 2022 | 51 | 39 |
| 2023 | 50 | 41 |
| 2024 | 31 | 33 |
| 2025 | 39 | 29 |
| 2026 | 11 | 13 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method and system for supporting memory functions during low power modes of a portable computing device (PCD)6 Oct 2026US 12,754,599 B2QUALCOMM Incorporated
- Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures8 Sep 2026US 12,730,562 B2
- Systems and methods for extending delay in self-timed memory28 Jul 2026US 12,694,924 B2Arm Limited
- Signal receiver with skew-tolerant strobe gating12 May 2026US 12,626,740 B2Rambus Inc.
- Memory component timed by programmably-selected clock edge7 Apr 2026US 12,597,454 B2Rambus Inc.
- Memory control component23 Jul 2026US 2026/0212905 A1Rambus Inc.
- Multi-channel memory16 Jul 2026US 2026/0204303 A1SK hynix Inc.
- Method and system for supporting memory functions during low power modes of a portable computing device (pcd)2 Jul 2026US 2026/0186554 A1QUALCOMM Incorporated
- Novel resource-optmized source synchronous data transfer2 Jul 2026US 2026/0187011 A1NXP USA, Inc.
- Hardware-based training for synchronous dynamic random-access memory28 May 2026US 2026/0148788 A1QUALCOMM Incorporated
Most cited
By later US patents
- Apparatus for synchronously generating clock signals in a data processing system430US 5,243,703 ARambus Inc. · 1993
- Vector processor system420US 8,356,144 B22013
- Memory system having synchronous-link DRAM (SLDRAM) devices and controller383US 6,442,644 B1Advanced Memory International, Inc. · 2002
- Synchronous interface for a nonvolatile memory331US 6,564,285 B1Intel Corporation · 2003
- Integrated circuit I/O using high performance bus interface325US 5,319,755 ARambus Inc. · 1994