Memory component timed by programmably-selected clock edge

A method of operation within an integrated-circuit memory component (memory IC), the method comprising:

• storing a sampling-edge value within a programmable register;
• receiving a timing signal via a timing signal input;
• and
• producing an output value consisting (i) exclusively of bits generated by sampling a signal at a first signaling interface in response to rising edges of the timing signal if the sampling-edge value specifies rising-edge sampling, and (ii) exclusively of bits generated by sampling the signal at the first signaling interface in response to falling edges of the timing signal if the sampling-edge value specifies falling-edge sampling.

An integrated-circuit memory component comprising:

• a programmable register to store a sampling-edge value;
• a timing input to receive a timing signal;
• and
• means for producing an output value consisting (i) exclusively of bits generated by sampling an inbound signal in response to rising edges of the timing signal if the sampling-edge value specifies rising-edge sampling, and (ii) exclusively of bits generated by sampling the inbound signal in response to falling edges of the timing signal if the sampling-edge value specifies falling-edge sampling.