Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures

A method, comprising:

• converting, by a multilevel signal encoder of a dynamic random access memory (DRAM) including a plurality of logic circuits each configured to input a plurality of bits into a plurality of multilevel signals corresponding to a plurality of symbols at a first device, wherein a count of the plurality of bits is greater than a count of the symbols;
• and
• driving the plurality of multilevel signals onto respective signal lines of an I/O bus to a second device via individual drivers, wherein each of the plurality of multilevel signals is configured to be one of more than two signal levels,
• wherein driving the plurality of multilevel signals onto the respective signal lines comprises controlling each of a plurality of sections of a driver associated with one of the plurality of multilevel signals, and
• wherein first and second control signals are used to control respective sections of the plurality of sections of the driver.

A method, comprising:

• determining, at a decoder, voltage levels of each of a plurality of multilevel signals received at a memory, wherein the plurality of multilevel signals corresponds to a plurality of symbols;
• and
• decoding the plurality of the multilevel signals based on the determined voltage levels to recover a plurality of bits,
• wherein determining the voltage levels of each of the plurality of multilevel signals received at the memory includes comparing a voltage of a first multilevel signal of the plurality of multilevel signals with a pair of reference voltages to provide a first pair of output signals, and further includes comparing a voltage level of a second multilevel signal of the plurality of multilevel signals with the pair of reference voltages to provide a second pair of output signals, and
• wherein only two reference voltages including the pair of reference voltages are used to determine signal levels of each of the plurality of multilevel signals.

A memory controller comprising:

• a driver circuit comprising:
• a plurality of logic circuits configured to convert a plurality of bits into a plurality of symbols, wherein a number of the plurality of bits is greater than a number of the plurality of symbols, wherein the plurality of bits includes eleven bits, and the plurality of symbols includes seven symbols corresponding to the eleven bits;
• and
• a plurality of drivers configured to drive the plurality of symbols onto a plurality of signal lines to provide the plurality of symbols to a memory device, wherein individual ones of the plurality of drivers are configured to drive more than two voltages;
• and
• an interface circuit including the driver circuit, the interface circuit configured to provide a first control signal and a second control signal to the memory device, wherein the first and second control signals are configured to control respective sections of a second driver circuit of the memory device.

A system comprising:

• a dynamic random access memory (DRAM) device configured to transmit and receive a plurality of symbols, wherein each of the plurality of symbols corresponds to two or more bits and each of the plurality of symbols is represented by a different voltage of a plurality of voltages, and comprising a first driver circuit including a multilevel signal encoder including a plurality of logic circuits, and the first driver circuit is a multi-leg driver that is divided into at least two sections, wherein a first control signal and a second control signal are used to control respective sections of the at least two sections of the first driver circuit;
• a memory controller configured to transmit and receive the plurality of symbols, the memory controller comprising:
• a circuit configured to convert a plurality of bits into a plurality of symbols;
• a plurality of driver circuits configured to transmit the plurality of symbols to the DRAM device, wherein individual driver circuits of the plurality of driver circuits are configured to drive more than two voltages and the plurality of driver circuits have a same impedance;
• and
• an I/O bus comprising a plurality of channels coupled between the DRAM device and the memory controller, wherein the plurality of symbols are transmitted on the plurality of channels, wherein a number of the plurality of channels is less than a number of bits represented by the plurality of symbols transmitted, and wherein the DRAM device is configured to receive the plurality of symbols from the memory controller from the I/O bus and convert the plurality of symbols into a plurality of bits, and store the plurality of bits in a memory array.

A system comprising:

• a dynamic random access memory (DRAM) device configured to transmit and receive a plurality of symbols, wherein each of the plurality of symbols corresponds to two or more bits and each of the plurality of symbols is represented by a different voltage of a plurality of voltages, wherein the two or more bits includes eleven bits, and the plurality of symbols includes seven symbols corresponding to the eleven bits;
• a memory controller configured to transmit and receive the plurality of symbols, the memory controller comprising:
• a circuit configured to convert a plurality of bits into a plurality of symbols;
• and
• a plurality of driver circuits configured to transmit the plurality of symbols to the DRAM device, wherein individual driver circuits of the plurality of driver circuits are configured to drive more than two voltages and the plurality of driver circuits have a same impedance;
• and
• an I/O bus comprising a plurality of channels coupled between the DRAM device and the memory controller, wherein the plurality of symbols are transmitted on the plurality of channels, wherein a number of the plurality of channels is less than a number of bits represented by the plurality of symbols transmitted, and wherein the DRAM device is configured to receive the plurality of symbols from the memory controller from the I/O bus and convert the plurality of symbols into a plurality of bits, and store the plurality of bits in a memory array.