Novel resource-optmized source synchronous data transfer

A method of operating an integrated circuit, comprising:

• receiving a first clock timing signal at an integrated circuit initiator component, where the first clock timing signal comprises a plurality of rising clock edges alternating with a plurality of falling clock edges;
• receiving a plurality of data bit signals at the integrated circuit initiator component, where the plurality of data bit signals comprises a first group of data bit signals and a second group of data bit signals;
• and
• transmitting the first clock timing signal and the plurality of data bit signals from the integrated circuit initiator component over a plurality of data path lines in a bus and to an integrated circuit target component by:
• launching the first group of data bit signals for transmission in parallel over a first subset of the plurality of data path lines in the bus to the integrated circuit target component in response to the plurality of rising clock edges of the first clock timing signal;
• and
• launching the second group of data bit signals for transmission in parallel over a second subset of the plurality of data path lines in the bus to the integrated circuit target component in response to the plurality of falling clock edges of the first clock timing signal;
• where the first subset of the plurality of data path lines in the bus is interleaved in alternating fashion with the second subset of the plurality of data path lines in the bus.

A System on Chip (SoC), comprising:

• a simplex, non-multiplexed interconnect bus comprising a plurality of data path lines and a clock path line;
• an initiator component core coupled to the simplex, non-multiplexed interconnect bus;
• and
• a target component core coupled to the simplex, non-multiplexed interconnect bus;
• where the initiator component is configured to transmit a clock timing signal and a plurality of data bit signals over the plurality of data path lines to the target component by:
• launching a first plurality of even data bit signals for transmission in parallel over a first subset of the plurality of data path lines to the target component in response to a plurality of rising clock edges of the clock timing signal;
• and
• launching the first plurality of odd data bit signals for transmission in parallel over a second subset of the plurality of data path lines to the target component in response to a plurality of falling clock edges of the clock timing signal;
• where the first subset of the plurality of data path lines in the bus is interleaved in alternating fashion with the second subset of the plurality of data path lines in the simplex, non-multiplexed interconnect bus;
• and
• where adjacent data path lines in the plurality of data path lines are formed with a minimum metal width and minimum metal spacing to prevent shielding wires from being located between the adjacent data path lines.