Systems and methods for extending delay in self-timed memory

A method comprising:

• determining a self-timed path (STP) circuit of a memory, wherein the STP circuit comprises at least one or more first delay elements of a plurality of delay elements on a first dummy wordline (DWL) and a dummy bitline (DBL) corresponding to write logic circuitry of the STP circuit;
• determining a logic delay of the STP circuit based at least on a delay associated with the write logic circuitry, wherein the logic delay corresponds to a pulse width;
• providing a first resistor-capacitor (RC) delay based on the logic delay, wherein:
• the first RC delay comprises a duration associated with one or more signals propagating through the first DWL and the DBL, and
• the first RC delay corresponds to a first augmentation of the pulse width;
• providing the STP circuit with an extended DWL;
• providing a second RC delay, wherein:
• the second RC delay comprises a duration associated with one of the one or more signals propagating through the extended DWL;
• and
• the second RC delay corresponds to a second augmentation of the pulse width, and
• performing a write operation on the memory based on a combination of the pulse width and the first and second augmentations of the pulse width.