Signal receiver with skew-tolerant strobe gating
AssigneeRambus Inc.
InventorsAndrew M. Fuller, Robert E. Palmer, Thomas J. Giovannini, Michael D. Bucher, Thoai Thai Le
Life of this patent
Estimating the term…
Abstract
A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.
Claims21
An integrated circuit component comprising:
- clock distribution circuitry to output a clock signal that establishes a first timing domain within the integrated circuit component;
- a timing signal input to receive a data-timing signal from a source external to the integrated circuit component, the data-timing signal having (i) a time-varying phase offset relative to the first timing domain, and (ii) active timing transitions that are preceded by one or more preamble transitions and succeeded by one or more postamble transitions;
- and
- timing-signal gating circuitry to:
- generate a gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset;
- and
- gate the data-timing signal with the gating pulse to generate a gated timing signal that lacks the one or more preamble transitions and the one or more postamble transitions.
A method of operation within an integrated circuit component, the method comprising:
- outputting, via clock distribution circuitry, a clock signal that establishes a first timing domain within the integrated circuit component;
- receiving, from a source external to the integrated circuit component, a data-timing signal having (i) a time-varying phase offset relative to the first timing domain, and (ii) active timing transitions that are preceded by one or more preamble transitions and succeeded by one or more postamble transitions;
- generating a gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset;
- and
- gating the data-timing signal with the gating pulse to generate a gated timing signal that lacks the one or more preamble transitions and the one or more postamble transitions.
An integrated circuit component comprising:
- means for generating a clock signal that establishes a first timing domain within the integrated circuit component;
- means for receiving, from a source external to the integrated circuit component, a data-timing signal having (i) a time-varying phase offset relative to the first timing domain, and (ii) active timing transitions that are preceded by one or more preamble transitions and succeeded by one or more postamble transitions;
- means for generating a gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset;
- and
- means for gating the data-timing signal with the gating pulse to generate a gated timing signal that lacks the one or more preamble transitions and the one or more postamble transitions.
Dependencies are inferred from the claim text.