Hardware-based training for synchronous dynamic random-access memory
AssigneeQUALCOMM Incorporated
InventorsFarrukh AQUIL, Boris Dimitrov ANDREEV
Life of this patent
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Abstract
Hardware-based training is described for synchronous dynamic random-access memory. In one aspect a memory includes a memory physical interface (PHY) of the memory coupled to a memory bus and configured to receive a received Pseudo-Random Binary Sequence (PRBS) through the memory bus at from a host PHY. A PRBS generator is configured to generate a generated PRBS and compare logic is configured to generate a score based on comparing the received PRBS to the generated PRBS. The memory PHY is further configured to send the score to the host PHY.
Claims20
A memory comprising:
- a memory physical interface (PHY) of a memory coupled to a memory bus and configured to receive a received Pseudo-Random Binary Sequence (PRBS) through the memory bus from a host PHY;
- a PRBS generator configured to generate a generated PRBS;
- and
- compare logic configured to generate a score based on comparing the received PRBS to the generated PRBS,
- the memory PHY further configured to send the score to the host PHY.
A method comprising:
- receiving a received Pseudo-Random Binary Sequence (PRBS) through a memory bus at a memory physical interface (PHY) from a host PHY;
- generating a generated PRBS at the memory PHY;
- comparing the received PRBS to the generated PRBS;
- generating a score based on comparing the received PRBS and the generated PRBS;
- and
- sending the score to the host PHY through the memory bus.
A memory apparatus comprising:
- means for receiving a received Pseudo-Random Binary Sequence (PRBS) through a memory bus at a memory physical interface (PHY) from a host PHY;
- means for generating a generated PRBS at the memory PHY;
- means for generating a score based on comparing the received PRBS to the generated PRBS;
- and
- means for sending the score to the host PHY through the memory bus.
Dependencies are inferred from the claim text.