Memory control component

A controller integrated circuit (“control IC”) to control one or more dynamic random memory access (DRAM) devices each of which (a) includes distinct first and second groups of memory banks and distinct first and second command/address (CA) interfaces, and (b) is configurable to support either (i) a first mode in which memory access operations within the first group of memory banks are carried out exclusively in response to memory access commands received via the first CA interface and memory access operations within the second group of memory banks are carried out exclusively in response to memory access commands received via the second CA interface or (ii) a second mode in which memory access operations within the first and second groups of memory banks are carried out exclusively in response to memory access commands received via the first CA interface, the control IC comprising:

• a first signaling interface to:
• transmit, to the first CA interface of a first DRAM device of the one or more DRAM devices, memory access commands that specify memory access operations solely within the first group of memory banks of the first DRAM device if the first DRAM device is configured to support the first mode;
• and
• transmit, to the first CA interface of the first DRAM device, memory access commands that specify memory access operations within both the first and second groups of memory banks of the first DRAM device if the first DRAM device is configured to support the second mode;
• and
• a second signaling interface to:
• transmit, to the second CA interface of the first DRAM device, memory access commands that specify memory access operations solely within the second group of memory banks of the first DRAM device if the first DRAM device is configured to support the first mode;
• and
• transmit, to the first CA interface of a second DRAM device of the one or more DRAM devices, memory access commands that specify memory access operations within both the first and second groups of memory banks of the second DRAM device if the second DRAM device is configured to support the second mode.

An integrated circuit memory controller, comprising:

• a circuit to indicate one of multiple command/address (CA) modes for controlling memory access within one or more dynamic random access memory (DRAM) devices each having first and second CA interfaces, the multiple CA modes including:
• a first mode to access first and second memory bank groups of a first DRAM device via the first and second CA interfaces, respectively, of the first DRAM device, and
• a second mode to access the first and second memory bank groups of the first DRAM device solely via the first CA interface of the first DRAM device and to access first and second memory bank groups of a second DRAM device solely via the first CA interface of the second DRAM device;
• and
• first and second interface circuits to transmit respective CA information, wherein:
• in the first mode:
• the first interface circuit transmits CA information to address the first bank group of the first DRAM device, and
• the second interface circuit transmits CA information to address the second bank group of the first DRAM device;
• and
• in the second mode:
• the first interface circuit transmits CA information to address both the first and second memory bank groups of the first DRAM device, and
• the second interface circuit transmits CA information to address both the first and second memory bank groups of the second DRAM device.