G11C 2211/5611
Multilevel memory cell with more than one control gate
G11C2211/5611 (Multilevel memory cell with more than one control gate) appears on 32 US grants and 11 published applications in this corpus.
Search patents in G11C- Granted patents
- 32
- Published applications
- 11
- Assignees
- 15
- Inventors
- 30
- Latest grant
- 2 Jan 2024
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 4 | 0 |
| 1993 | 1 | 0 |
| 1994 | 4 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 2 | 0 |
| 1999 | 2 | 0 |
| 2000 | 1 | 0 |
| 2001 | 0 | 1 |
| 2002 | 0 | 0 |
| 2003 | 3 | 2 |
| 2004 | 2 | 2 |
| 2005 | 0 | 0 |
| 2006 | 1 | 1 |
| 2007 | 1 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 2 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 2 |
| 2014 | 0 | 0 |
| 2015 | 2 | 0 |
| 2016 | 0 | 0 |
| 2017 | 1 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 1 | 0 |
| 2021 | 1 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 1 |
| 2024 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- One transistor memory bitcell with arithmetic capability2 Jan 2024US 11,862,282 B2Ceremorphic, Inc.
- Memory cell arrangement and methods thereof30 Nov 2021US 11,189,331 B1Ferroelectric Memory GmbH
- Flash memory with multiple control gates and flash memory array device made thereof14 Apr 2020US 10,622,451 B1National Cheng Kung University
- Method of operating flash memory unit2 May 2017US 9,640,252 B1Shanghai Huahong Grace Semiconductor Manufacturing Corporation
- Memory apparatus with gated phase-change memory cells21 Jul 2015US 9,087,574 B2International Business Machines Corporation
- One Transistor Memory Bitcell with Arithmetic Capability22 Jun 2023US 2023/0197121 A1Ceremorphic, Inc.
- Memory apparatus with gated phase-change memory cells5 Dec 2013US 2013/0322166 A1International Business Machines Corporation
- Memory apparatus with gated phase-change memory cells5 Dec 2013US 2013/0322168 A1International Business Machines Corporation
- Dual-gate memory device with channel crystallization for multiple levels per cell (mlc)30 Jul 2009US 2009/0191680 A1
- Dual-gate memory device with channel crystallization for multiple levels per cell (mlc)9 Apr 2009US 2009/0090913 A1
Most cited
By later US patents
- Multigate semiconductor device with vertical channel current and method of fabrication396US 6,580,124 B1Matrix Semiconductor, Inc. · 2003
- Multigate semiconductor device with vertical channel current and method of fabrication307US 6,677,204 B2Matrix Semiconductor, Inc. · 2004
- Memory with isolatable expandable bit lines211US 5,677,867 A1997
- Non-volatile memory circuits and architecture45US 5,278,785 A1994
- Preventing dielectric thickening over a channel area of a split-gate transistor39US 6,136,652 A2000