Memory apparatus with gated phase-change memory cells
AssigneeInternational Business Machines Corporation
InventorsGael Close, Daniel Krebs
Life of this patent
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Abstract
A memory apparatus includes a plurality of gated phase-change memory cells having s≧2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only.
Claims14
1-13. (canceled)
A method of operating a memory apparatus having a plurality of gated phase-change memory cells having s≧2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain, the method comprising:
- applying, using a bias voltage generator, a bias voltage to the gate of each cell;
- and
- using a controller, configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only.
Dependencies are inferred from the claim text.