Non-volatile memory circuits and architecture

A non-volatile memory array comprising:

• address receiving means;
• a signal processing means;
• a plurality of array sections each comprising a plurality of split gate memory cells each including a floating gate and having asymmetry between their drain to source current and source to drain current arranged in a plurality of rows and adjacent columns;
• each column having a first bit line and a second bit line, said memory cells of even numbered rows connected with their drains to said first bit line and with their sources to said second bit line, and said memory cells of odd numbered rows connected with their drains to said second bit line and with their sources to said first bit line, said memory cells are operable to couple or to decouple said bit lines;
• column address circuitry operable to randomly address a selected one of said columns in each of said sections;
• row address circuitry operable to randomly address a selected one of said rows in each of said sections;
• for each of said sections a cross-point switch operable to route said first bit line to said signal processing means and to route said second bit line to a first reference voltage when an even numbered row is selected for read operation;
• said cross-point switch also operable to route said first bit line to a programming reference voltage and to route said second bit line to a second reference voltage when an even numbered row is selected for programming operation;
• said cross-point switch also operable to route said second bit line to said signal processing means and to route said first bit line to said first reference voltage when an odd numbered row is selected for read operation;
• and
• said cross-point switch also operable to route said second bit line to said programming reference voltage and to route said first bit line to said second reference voltage when an odd numbered row is selected for programming operation.

A non-volatile memory array comprising:

• address receiving means;
• a signal processing means;
• a plurality of array sections each comprising a plurality of split gate memory cells each including a floating gate and having asymmetry between their drain to source current and source to drain current arranged in a plurality of rows and columns;
• each of said column having a first bit line and a second bit line, said memory cells of even numbered rows connected with their drains to said first bit line and with their sources to said second bit line, and said memory cells of odd numbered rows connected with their drains to said second bit line and with their sources to said first bit line, said memory cells are operable to couple or to decouple said bit lines;
• column address circuitry;
• row address circuitry operable to randomly address a selected one of said rows in each of said sections;
• for each of said sections a cross-point switch operable to route said second bit line to said signal processing means and to route said first bit line to a first reference voltage when an even numbered row is selected for read operation;
• said cross-point switch also operable to route said first bit line to a programming reference voltage and to route said second bit line to a second reference voltage when an even numbered row is selected for programming operation;
• said cross-point switch also operable to route said first bit line to said signal processing means to route said second bit line to said first reference voltage when an odd numbered row is selected for read operation;
• and
• said cross-point switch also operable to route said second bit line to said programming reference voltage and to route said first bit line to said second reference voltage when an odd numbered row is selected for programming operation.

A memory array comprising:

• a plurality of array sections each comprising a plurality of memory cells arranged in a plurality of rows and plurality of columns forming a plurality of pairs of adjacent odd numbered column and even numbered column;
• each column having a first bit line and a second bit line, said at least one memory cell programmable to couple or to decouple said first bit line to said second bit line;
• a latch circuit exclusively associated with each one of said pair of columns;
• whereby said latch is operable to be coupled either to said first bit line of said even numbered column or to said first bit line of said odd numbered column within said associated pair, and said latch is operable in a manner that prevents exchange of data between said latch and pairs of said columns that are not associated with said latch.

A data storage means comprising;

• an input FET transistor coupled with its drain to an input line and its source to a storage node;
• a first inverter connected with its input to said storage node and its output to an output line;
• a second inverter including:
• (a) a first transistor with a first conductivity type channel, and (b) a second and a third transistors each with a second conductivity type channel;
• said first transistor and said third transistor having their gates connected to said output line;
• a clock input line connected to the gates of said input FET and said second transistor;
• said first transistor connected with its source to a first reference voltage and its drain to said storage node;
• said second transistor connected with its drain to said storage node and its source to a second node;
• and
• said third transistor connected with its drain to said second node and its source to a second reference voltage.

A power switch includes in a programmable non-volatile memory chip including:

• a VCC receiving means;
• a VPP receiving means;
• a VSS receiving means;
• a current mirror having a reference branch, a first output branch and a second output branch;
• a first FET transistor connecting said VCC means and said first output branch;
• a second FET transistor connecting said VCC means and said second output branch;
• said reference branch, said first FET and said second FET having a common control input;
• said power switch operable to supply VCC voltage to said first and second outputs during read operations of said memory chip;
• and
• said power switch operable to supply VPP voltage to said first and second outputs during write operations of said memory chip.

A non-volatile memory formed on a semiconductor substrate for storing analog signals comprising:

• address receiving means;
• a signal processing means;
• a memory array comprising a plurality of physical memory cells arranged in a plurality of rows and columns;
• column address circuitry;
• row address circuitry operable to randomly address a selected one of said rows;
• and
• a digital to analog converter operable to receive digital data and program analog data that has at least three logical states in each one of said physical memory cells of said memory array.

An address decoder circuit for decoding the row address of an EEPROM including rows and columns of memory cells comprising:

• a word line driver having an input and an output that is coupled to a memory row;
• a mode select multiplexer having a first and a second control inputs, a first and a second data input and a data output coupled to said word line driver;
• a logical gate for selection having plurality of inputs coupled to row address lines and an output coupled to the first data input of said mode select multiplexer;
• said logical gate having power supply between a first reference voltage and a second reference voltage;
• and
• a phase feedback inverter whose input is coupled to the output of said logical gate and whose output is coupled to said second data input of said mode select multiplexer.