US 11,189,331 B1Granted

Memory cell arrangement and methods thereof

AssigneeFerroelectric Memory GmbH

InventorsAntoine Benoist, Marko Noack

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Abstract

A memory cell arrangement is provided that may include: at least one memory cell and a read-out circuit. The memory cell includes a first terminal, a second terminal, a third terminal, and a field-effect transistor structure being connected to the first terminal, the second terminal, and the third terminal. The read-out circuit is configured to carry out a read-out operation to read out a memory state of the memory cell, the read-out operation including: providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated, and sensing the leakage current to determine the memory state of the memory element.

Claims37

Dependent claims

A memory cell arrangement, comprising:

a memory cell, the memory cell comprising:
a first terminal;
a second terminal;
a third terminal;
a field-effect transistor structure comprising a first source/drain region connected to the first terminal, a second source/drain region connected to the second terminal, and a gate structure connected to the third terminal, wherein the gate structure comprises a memory element;
and
a read-out circuit configured to carry out a read-out operation to read out a memory state of the memory element, the read-out operation comprising:
providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated;
and
sensing the leakage current to determine the memory state of the memory element;
wherein the field-effect transistor structure comprises a channel region extending from the first source/drain region to the second source/drain region, wherein the channel region is in a non-conductive state in the case that the field-effect transistor structure is in the high-resistivity state, wherein, in the non-conductive state, a resistance value associated with the channel region is greater than 1 MΩ.

8 more elements

A memory cell arrangement, comprising:

a memory cell, the memory cell comprising:
a first terminal;
a second terminal;
a third terminal;
a field-effect transistor structure comprising a first source/drain region connected to the first terminal, a second source/drain region connected to the second terminal, and a gate structure connected to the third terminal, wherein the gate structure comprises a memory element;
and
a read-out circuit configured to carry out a read-out operation to read out a memory state of the memory element, the read-out operation comprising:
providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated;
sensing the leakage current to determine the memory state of the memory element;
and
a plurality of additional memory cells, each memory cell of the plurality of additional memory cells comprising:
a first terminal;
a second terminal;
a third terminal;
a field-effect transistor structure comprising a first source/drain region connected to the first terminal, a second source/drain region connected to the second terminal, and a gate structure connected to the third terminal, wherein the gate structure comprises a memory element,
wherein the memory cell and each of the plurality of additional memory cells have a first distribution of first threshold voltage values associated therewith in the case that the respective memory cells are in a first memory state and a second distribution of second threshold voltage values associated therewith in the case that the respective memory cells are in a second memory state,
wherein a gate of the field-effect transistor structure has a footprint such that the first distribution and the second distribution at least partially overlap,
wherein the footprint is less than 0.1 μm2.

15 more elements

A memory cell arrangement, comprising:

a memory cell, the memory cell comprising:
a first terminal;
a second terminal;
a third terminal;
a field-effect transistor structure comprising a first source/drain region connected to the first terminal, a second source/drain region connected to the second terminal, and a gate structure connected to the third terminal, wherein the gate structure comprises a memory element;
and
a read-out circuit configured to carry out a read-out operation to read out a memory state of the memory element, the read-out operation comprising:
providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated;
sensing the leakage current to determine the memory state of the memory element;
and
wherein sensing the leakage current to determine the memory state of the memory element comprises sensing a sum of a first leakage current portion that flows through the first terminal and a second first leakage current portion that flows through the second terminal, and determining the memory state of the memory element based on the sum of the first leakage current portion and the second leakage current portion.

8 more elements

A memory cell arrangement, comprising:

a memory cell, the memory cell comprising:
a first terminal;
a second terminal;
a third terminal;
a field-effect transistor structure comprising a first source/drain region connected to the first terminal, a second source/drain region connected to the second terminal, and a gate structure connected to the third terminal, wherein the gate structure comprises a memory element;
and
a read-out circuit configured to carry out a read-out operation to read out a memory state of the memory element, the read-out operation comprising:
providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated;
and
sensing the leakage current to determine the memory state of the memory element,
wherein a gate of the field-effect transistor structure has a footprint less than 0.1 μm2.

8 more elements

Dependencies are inferred from the claim text.