Memory with isolatable expandable bit lines

A memory array matrix architecture for compactness including plurality of memory cell rows oriented along an X direction and memory cell columns that include elongated bit lines that are oriented along a Y direction wherein each memory cell includes an field effect transistor (FET transistor) having a gate, a drain region and source region of a first conductivity type diffusion formed on a second conductivity type substrate, said memory array further comprising:

• said bit lines formed of said first conductivity type diffusion and having a first set of access bit-lines and a second set of bit-lines that are interleaved so that every bit line from said second set is disposed between two bit lines from said first set one to its right side and one to its left side and every bit line from said first set is disposed between two bit lines from said second set and said bit lines are oriented along said Y direction that is perpendicular to said X direction;
• said each bit line from said second set of bit lines comprising a first, a second, a third and a fourth bit line segments that are selectively connected to each other by means of segment border FET transistors;
• said segment border FET transistors are arranged so that a first segment border FET connects said first and second segments and a second segment border FET connects said second and third segments and a third segment border FET connects said third and fourth segments when desired;
• a first select transistor selectively couples said each second segment to an access bit line to its right side and a second select transistor selectively couples each said second segments to an access bit line to its left side and wherein the gates of said first select transistors are connected to each other by a first conductive select line and wherein the gates of said second select transistors are connected to each other by a second conductive select line;
• a third select transistor selectively couples said each third segment to an access bit line to its fight side and a fourth select transistor selectively couples each said third segments to an access bit line to its left side and wherein the gates of said third select transistors are connected to each other by a third conductive select line and wherein the gates of said fourth select transistors are connected to each other by a fourth conductive select line;
• a fifth select transistor selectively couples said each fourth segment to an access bit line to its right side and a sixth select transistor selectively couples each said fourth segments to an access bit line to its left side and wherein the gates of said fifth select transistors are connected to each other by a fifth conductive select line and wherein the gates of said sixth select transistors are connected to each other by a sixth conductive select line;
• said first and second select transistors are located adjacent said first segment border transistor having no memory cells therebetween and at least two rows of said memory cells are placed between said first and second select transistors and said second segment border transistors so said drain and source regions are in contact with said bit lines in a manner to selectively couple or decouple to a desired degree said bit lines;
• said third and fourth select transistors are located adjacent said second segment border transistor having no memory cells therebetween and at least two rows of said memory cells are placed between said third and fourth select transistors and said third segment border transistors so said drain and source regions are in contact with said bit lines in a manner to selectively couple or deeouple to a desired degree said bit lines;
• and said fifth and sixth select transistors are located adjacent said third segment border transistor having no memory cells therebetween.

Shield insulating gate apparatus for reducing isolation spacing between impurities bit lines regions of a first conductivity type in a memory array formed on a semiconductor substrate of a second conductivity type including;

• a first impurities region;
• a second impurities region;
• a third impurities region;
• a first field effect transistor (FET transistor) having its drain connected to said first impurities region and its source connected to said second impurities region;
• a second FET transistor having its drain connected to said first impurities region and its source connected to said third impurities region;
• and
• a conductor connecting the gates of said FET transistors to a reference voltage whose voltage magnitude is lower than the magnitude of the threshold voltage of either of said FET transistors thereby making said transistors non-conducting during all operating modes of said memory array.

A memory array matrix including plurality of memory cell rows and memory cell columns that include bit lines wherein each memory cell includes an field effect transistor (FET transistor) having drain region and source region of a first conductivity type formed on a second conductivity type substrate;

• said bit lines comprising a first set of bit-lines and a second set of bit-lines that are interleaved;
• said FET transistor in said memory cell along each column connected by a first conductivity type impurities bit line region;
• said array is organized so that a first shield means comprising the following (a) to (f) elements;
• (a) a first impurities region;
• (b) a second impurities region;
• (c) a third impurities region;
• (d) a first FET transistor having its drain connected to said first impurities region and its source connected to said second impurities region;
• (e) a second FET transistor having its drain connected to said first impurities region and its source connected to said third impurities region;
• and (f) a conductor connecting the gates of said FET transistors to a reference voltage whose voltage magnitude is lower than the magnitude of the threshold voltage of either of said FET transistors thereby making said transistors non-conducting during all operating modes of said memory array, so that said first shield means is connected to a first bit-line from said second set of bit-lines every Q memory cell rows so that said first bit line from said second set of bit lines constitutes a drain and two adjacent bit-line regions of said first set of bit lines constitute sources of FET transistors in said first shield means;
• and
• said array is farther organized so that a second shield means comprising the same elements (a) to (f) of said first shield means and is connected to a first bit-line from said first set of bit-lines every P memory cell rows so that said first bit-line from said first set of bit-lines constitutes a drain and two adjacent bit line regions of said second set of bit-lines constitute sources of FET transistors in said second shield means.