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US 11,862,282 B2Granted
One transistor memory bitcell with arithmetic capability
AssigneeCeremorphic, Inc.
InventorsNeelam Surana, Robert F. Wiser
Life of this patent
Estimating the term…
Abstract
A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source connected in parallel, and when read, generate a current provided to a current comparator amplifier (CCA) which is compared to a reference current Iref to generate an output which is at least one of a logical AND, logical NAND, logical OR, logical NOR, or logical exclusive OR (XOR).
Claims20
An arithmetic memory comprising:
- a first Single Transistor Static Random Access Memory (STSRAM) having a source, drain, and gate, and storing a charge value which modifies a conductivity from the drain to the source when the gate is enabled;
- a second STSRAM having a source, drain, and gate, and storing a charge value which modifies a conductivity from the drain to the source when the gate is enabled;
- a select line (SL) coupled to the first STSRAM drain and also to the second STSRAM drain;
- a current comparator amplifier (CCA) having a noninverting input and an inverting input, the CCA asserting a binary output when a sum of currents applied to the CCA noninverting input is greater than a current Iref applied to the inverting input of the CCA;
- a Bit Line (BL) node coupled to the first STSRAM source, the second STSRAM source, and to the noninverting input of the CCA;
- the CCA output configured to output at least one of an OR, NOR, AND, or NAND operation, and where the charge value of the first STSRAM and the charge value of the second STSRAM provides the sum of currents.
3 more elements
A logic memory storing two charges and performing a logic operation on the two charges, the logic memory comprising:
- a first Single Transistor Static Random Access Memory (STSRAM) having a source, drain, and gate, and storing a charge value which modifies a conductivity from the drain to the source when the gate is enabled;
- a second STSRAM having a source, drain, and gate, and storing a charge value which modifies a conductivity from the drain to the source when the gate is enabled;
- a select line (SL) coupled to the first STSRAM drain and also to the second STSRAM drain;
- a Bit Line (BL) node coupled to the first STSRAM source, the second STSRAM source, and to a noninverting input of a current comparator amplifier (CCA) generating a binary result by comparing a current IBL applied to the noninverting input of the CCA to a current Iref applied to an inverting input of the CCA, the inverting input of the CCA coupled to a current source Iref;
- a current IBL through the first STSRAM and second STSRAM thereby having:
- a first value when a charge is not stored in the first STSRAM and the second STSRAM;
- a second value with a charge is stored in one of the first STSRAM or the second STSRAM;
- a third value when a charge is stored in both the first STSRAM and the second STSRAM;
- the CCA having an output performing a logic operation governed by a setting of Iref and selection of a polarity of the output.
6 more elements
A memory performing a logical AND or logical NAND operation, the memory comprising:
- a first Single Transistor Static Random Access Memory (STSRAM) having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled;
- a second STSRAM having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled;
- a select line (SL) coupled to the first STSRAM drain and also to the second STSRAM drain;
- a Bit Line (BL) node coupled to the first STSRAM source, the second STSRAM source, and to a noninverting input of a current comparator amplifier (CCA), the CCA having an inverting input coupled to a current source Iref, the CCA generating a binary output by comparing a combined current IBL from the first STSRAM and second STSRAM delivered to the noninverting input of the CCA to a current Iref delivered to the inverting input of the CCA;
- Iref being set to a current Iref11 which is greater than IBL when only one of the first STSRAM or second STSRAM has a stored charge;
- the first STSRAM and the second STSRAM having respective stored charge which generate to the noninverting input of the CCA:
- a first current when a charge is not stored in the first STSRAM and the second STSRAM;
- a second current when a charge is stored in one of the first STSRAM or the second STSRAM;
- a third current when a charge is stored in both the first STSRAM and the second STSRAM.
6 more elements
A memory performing a logical exclusive or (XOR) operation, the memory comprising:
- a first Single Transistor Static Random Access Memory (STSRAM) having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled;
- a second STSRAM having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled;
- a select line (SL) coupled to the first STSRAM drain and also to the second STSRAM drain;
- a first current comparator amplifier (CCA) having an inverting input and a noninverting input, the first CCA generating a binary output by comparison of a current applied to the inverting input and a current applied to the noninverting input;
- a second current comparator amplifier (CCA) having an inverting input and a noninverting input, the second CCA generating a binary output by comparison of a current applied to the inverting input and a current applied to the noninverting input;
- a Bit Line (BL) node coupled to the first STSRAM source, the second STSRAM source, and to the noninverting input of the first CCA and also to the inverting input of the second CCA;
- the first CCA inverting input coupled to a first current source Iref1, the second CCA noninverting input coupled to a second current source Iref2;
- the first CCA output and second CCA output coupled to an AND gate forming an exclusive OR logical output.
5 more elements
Dependencies are inferred from the claim text.