US 6,136,652 AGranted

Preventing dielectric thickening over a channel area of a split-gate transistor

OwnerEmanuel Hazaniinventor

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Abstract

A process for a split-gate transistor (e.g. flash-EEPROM cell), which includes a channel's drain-area, a first insulator disposed over the drain-area and a first gate disposed over the first insulator, and a control (select) gate is insulatively disposed over the channel's source-area and over a channel's gap-area located between the drain area and source area. It includes growing a second thin thermal oxide to be in contact with the first gate and the channel's source-area and gap-area that is adjacent he channel's drain-area, depositing TEOS based LPCVD oxide on the second oxide and then depositing the control gate on the first gate and over the channel's source and gap areas. It prevents the formation of an oxide beak under the first gate, thereby the first insulator has a uniform thickness. The polysilicon of the control gate conforms to the side wall of the first gate and does not protrude under the first gate. The transistor programs efficiently, is reliable, has low manufacture cost and is physically and electrically down scalable.

Claims31

Dependent claims

A process for fabricating a field-effect semiconductor memory device comprising the steps of:

(a) providing a structure including:
(i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region and a spaced apart source region of said device, and said channel is situated between said drain region and source region and having a drain area adjacent said drain region and having source area adjacent said source region;
(ii) a first member disposed over said drain area and over at least a portion of said drain region of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area;
(b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel;
(c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall;
and
(d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area thereby said first conductive layer and said second conductive layer forming a floating gate and a control gate respectively of an electrically programmable non-volatile transistor.

4 more elements

A process for fabricating a field-effect semiconductor device comprising the steps of:

(a) providing an apparatus including:
(i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region of said device, and said channel having a drain area adjacent said drain region and having a source area;
(ii) a first member disposed over said drain area and over at least a portion of said drain region of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area;
(b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel;
(c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall;
and
(d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area.

4 more elements

A process for fabricating a field-effect semiconductor device comprising the steps of:

(a) providing a structure including:
(i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region of said device, and said channel having a drain area adjacent said drain region and having a source area;
(ii) a first member disposed over said drain area of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area;
(b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel;
(c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall;
and
(d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area.

4 more elements

A process for fabricating a field-effect semiconductor device comprising the steps of:

(a) providing a structure including:
(i) a semiconductor substrate of a first-conductivity type having first-conductivity type first region that has a first surface, a first area and an adjacent second area, and a first second-conductivity type second region;
(ii) a first member disposed over first area of said first region and comprising a first dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first dielectric layer wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said first conductivity type first region and said first sidewall is laterally spaced apart from said second-conductivity type second region and is adjacent said first-conductivity type second area;
(b) growing and retaining a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first-conductive layer to a third thickness and by oxidation of said first-conductivity type second area;
and
(c) depositing a third dielectric layer to be in permanent contact with and conformal to said second thermal oxide to form a first gap-of-insulation-wall that is perpendicular to said first surface of said first-conductivity type first region of said substrate and so that said first gap-of-insulation-wall is in contact with said first sidewall of said first conductive layer;
(d) forming a second second-conductivity type second region to form a source region in said substrate so that said source region is adjacent said second area and is laterally spaced apart from said first second-conductivity type second region;
and
(e) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over said second area, thereby said first second-conductivity type second region forms a drain region of said device, and said first conductivity type first region forms a channel region of said device, said first area and a second area of said channel forming drain area and source area respectively of said channel, and said first dielectric layer forms a first gate oxide, and said first conductive layer and said second conductive layer forming a floating gate and a control gate respectively of a programmable non-volatile device.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/890,724Filed 9 Jul 1997 · division
Priority: 10 Jul 1989
Granted: 24 Oct 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
G11C 11/5621
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge storage in…
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 11/5635
Programming or writing circuits; Data input circuits: erasing circuits

Family

Serial377,311Parent of this continuation-in-part · filed 10 Jul 1989
Serial713,995Parent of this division · filed 12 Jun 1991
Serial179,587Parent of this continuation-in-part · filed 10 Jan 1994
Serial497,608Parent of this division · filed 30 Jun 1995
US 5,677,867 AParent of this division
US 5,440,518 AParent of this continuation-in-part
US 5,278,785 AParent of this division
US 5,099,297 AParent of this continuation-in-part
US 6,136,652 AThis patent

From the US filing history. Foreign family members aren’t listed.