G11C 2013/0076
Write operation performed depending on read result
Official title: {Write operation performed depending on read result}
G11C2013/0076 (Write operation performed depending on read result) appears on 350 US grants and 380 published applications in this corpus.
Search patents in G11C- Granted patents
- 350
- Published applications
- 380
- Assignees
- 96
- Inventors
- 594
- Latest grant
- 17 Mar 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2003 | 2 | 4 |
| 2004 | 3 | 2 |
| 2005 | 0 | 1 |
| 2006 | 0 | 8 |
| 2007 | 4 | 5 |
| 2008 | 7 | 18 |
| 2009 | 8 | 23 |
| 2010 | 17 | 27 |
| 2011 | 23 | 23 |
| 2012 | 24 | 20 |
| 2013 | 24 | 27 |
| 2014 | 28 | 30 |
| 2015 | 29 | 31 |
| 2016 | 27 | 25 |
| 2017 | 30 | 13 |
| 2018 | 16 | 21 |
| 2019 | 27 | 16 |
| 2020 | 17 | 22 |
| 2021 | 19 | 23 |
| 2022 | 17 | 19 |
| 2023 | 14 | 8 |
| 2024 | 7 | 3 |
| 2025 | 5 | 6 |
| 2026 | 2 | 5 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Bit line timing based cell tracking quick pass write for programming non-volatile memory apparatuses17 Mar 2026US 12,580,023 B2SanDisk Technologies LLC
- Management of unmapped allocation units of a memory sub-system3 Feb 2026US 12,541,398 B2Micron Technology, Inc.
- Apparatus, method and system to implement a dual VDM scheme on a three-dimensional memory architecture25 Nov 2025US 12,481,454 B2Intel Corporation
- Two-terminal metastable mixed-conductor memristive devices18 Feb 2025US 12,229,652 B2International Business Machines Corporation
- Cross-point memory read technique to mitigate drift errors18 Feb 2025US 12,230,346 B2Intel Corporation
- Memory device and operating method of the memory device9 Jul 2026US 2026/0196265 A1SK hynix Inc.
- Memory apparatus, memory system, and operation method of memory system4 Jun 2026US 2026/0155175 A1SK hynix Inc.
- Semiconductor device and writing method14 May 2026US 2026/0134901 A1Renesas Electronics Corporation
- Method for modifying a conductance value of a phase change memory cell during an inference cycle30 Apr 2026US 2026/0120760 A1Commissariat A L' Energie Atomique Et Aux Energies Alternatives
- Hiding information in memory cells5 Mar 2026US 2026/0065986 A1Infineon Technologies AG
Most cited
By later US patents
- Technique and apparatus for performing write operations to a phase change material memory device203US 6,545,907 B1Ovonyx, Inc. · 2003
- Dual write cycle programmable conductor memory system and method of operation67US 6,731,528 B2Micron Technology, Inc. · 2004
- Non-volatile semiconductor memory device allowing concurrent data writing and data reading60US 7,286,394 B2Renesas Technology Corp. · 2007
- Refreshing memory cells of a phase change material memory device53US 6,768,665 B2Intel Corporation · 2004
- Method and apparatus to reset a phase change memory and switch (PCMS) memory cell53US 8,462,537 B2Intel Corporation · 2013