Cross-point memory read technique to mitigate drift errors
AssigneeIntel Corporation
InventorsHemant P. Rao, Raymond W. Zeng, Prashant S. Damle, Zion S. Kwok, Kiran Pangal, Mase J. Taub
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Abstract
A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.
Claims20
A memory device comprising:
- an array of cross-point memory cells, each of the cross-point memory cells including a memory element and a switch element;
- and
- circuitry to:
- apply a first voltage across the cross-point memory cell, wherein the first voltage has a first magnitude;
- after application of the first voltage across the cross-point memory cell, apply a second voltage across the cross-point memory cell, wherein the second voltage has a second magnitude that is lower than the first magnitude;
- and
- determine a state of the cross-point memory cell based on a response of the cross-point memory cell to at least the second voltage, wherein:
- the state of the cross-point memory cell is one of at least three states, including a first state, a second state with a first threshold voltage distribution higher than the first state, and a third state with a second threshold voltage distribution higher than the second state, and
- the first magnitude is between expected threshold voltages for the second state and the third state.
A method of reading a cross-point memory cell, the method comprising:
- applying a first voltage across the cross-point memory cell, wherein the first voltage has a first magnitude;
- after applying the first voltage across the cross-point memory cell, applying a second voltage across the cross-point memory cell, wherein the second voltage has a second magnitude that is lower than the first magnitude;
- and
- determining a state of the cross-point memory cell based on a response of the cross-point memory cell to at least the second voltage, wherein:
- the state of the cross-point memory cell is one of at least three states, including a first state, a second state with a first threshold voltage distribution higher than the first state, and a third state with a second threshold voltage distribution higher than the second state, and
- the first magnitude is between expected threshold voltages for the second state and the third state.
A system comprising:
- a memory controller;
- and
- a memory die in a same package as the memory controller, the memory die comprising:
- an array of cross-point memory cells, each of the cross-point memory cells including a memory element and a switch element;
- and
- circuitry to:
- apply a first voltage across the cross-point memory cell, wherein the first voltage has a first magnitude;
- after application of the first voltage across the cross-point memory cell, apply a second voltage across the cross-point memory cell, wherein the second voltage has a second magnitude that is lower than the first magnitude;
- and
- determine a state of the cross-point memory cell based on a response of the cross-point memory cell to at least the second voltage, wherein:
- the state of the cross-point memory cell is one of at least three states, including a first state, a second state with a first threshold voltage distribution higher than the first state, and a third state with a second threshold voltage distribution higher than the second state, and
- the first magnitude is between expected threshold voltages for the second state and the third state.
Dependencies are inferred from the claim text.