Bit line timing based cell tracking quick pass write for programming non-volatile memory apparatuses

A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states and disposed in memory holes each coupled to one of a plurality of bit lines, the controller configured to:

• instruct the memory apparatus to apply a plurality of program pulses to selected ones of the plurality of word lines;
• for each one of the memory cells, instruct the memory apparatus to determine when the threshold voltage of the one of the memory cells exceeds a lower verify level of one of the plurality of data states targeted and maintain a respective count of a number of the plurality of program pulses subsequently applied to the one of the memory cells before the one of the memory cells reaches a lockout state, each of the plurality of program pulses having a program pulse duration divided into a plurality of program pulse phases;
• and
• for each one of the memory cells, instruct the memory apparatus to set a voltage of one of the plurality of bit lines coupled to the one of the memory cells at a stepped up level as a function of the respective count and according to each of the plurality of program pulse phases in which the voltage is set to the stepped up level and differently based on the one of the memory cells being in an inhibit zone or not, the one of the memory cells being in the inhibit zone with the threshold voltage greater than a higher verify level of the one of the plurality of data states targeted, and the higher verify level being greater than the lower verify level.

A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states and disposed in memory holes each coupled to one of a plurality of bit lines;

• the method comprising the steps of:
• applying a plurality of program pulses to selected ones of the plurality of word lines;
• for each one of the memory cells, determining when the threshold voltage of the one of the memory cells exceeds a lower verify level of one of the plurality of data states targeted and maintaining a respective count of a number of the plurality of program pulses subsequently applied to the one of the memory cells before the one of the memory cells reaches a lockout state, each of the plurality of program pulses having a program pulse duration divided into a plurality of program pulse phases;
• and
• for each one of the memory cells, setting a voltage of one of the plurality of bit lines coupled to the one of the memory cells at a stepped up level as a function of the respective count and according to each of the plurality of program pulse phases in which the voltage is set to the stepped up level and differently based on the one of the memory cells being in an inhibit zone or not, the one of the memory cells being in the inhibit zone with the threshold voltage greater than a higher verify level of the one of the plurality of data states targeted, and the higher verify level being greater than the lower verify level.