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US 2026/0155175 A1Published application
Memory apparatus, memory system, and operation method of memory system
AssigneeSK hynix Inc.
InventorsBeom Seok LEE, Myoungsub KIM, Ung Hee PARK, Jae Hyuk PARK, Sang Chul OH, Won Jun LEE
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Abstract
A memory system includes: a memory apparatus including a plurality of memory cells; and a controller that controls a curing operation to be performed on a first memory cell among the plurality of memory cells when the number of access operations performed on the first memory cell exceeds a preset number of times.
Claims34
A memory system comprising:
- a memory apparatus including a plurality of memory cells;
- and
- a controller that controls a curing operation to be performed on a first memory cell among the plurality of memory cells when the number of access operations performed on the first memory cell exceeds a preset number of times.
A memory system comprising:
- a memory apparatus including a plurality of memory cells;
- and
- a controller that controls a curing operation to be performed on a first memory cell among the plurality of memory cells when an error rate of the first memory cell exceeds a preset value.
An operation method of a memory system, comprising:
- managing numbers of access operations for a plurality of memory cells;
- determining whether a first memory cell exists among the plurality of memory cells, the number of access operations performed on the first memory cell exceeding a set number of times;
- determining data stored in the first memory cell when the first memory cell exists;
- and
- performing a curing operation on the first memory cell according to a result of the determining.
2 more elements
An operation method of a memory system, comprising:
- correcting and managing an error in data output from a plurality of memory cells;
- determining states of the plurality of memory cells each according to an error rate calculated in the managing;
- and
- performing a curing operation based on the error rate.
1 more element
A memory apparatus comprising:
- a cell array including a plurality of memory cells;
- a write circuit that stores data in at least first memory cell of the plurality of memory cells on the basis of a write command;
- and
- a read circuit that outputs data from at least second memory cell of the plurality of memory cells on the basis of a read command,
- wherein the write circuit cures at least third memory cell of the plurality of memory cells on the basis of a curing command.
2 more elements
Dependencies are inferred from the claim text.