Apparatus, method and system to implement a dual VDM scheme on a three-dimensional memory architecture

A system comprising:

• a memory array including bitlines (BLs), wordlines (WLs), first memory cells and second memory cells, the first memory cells and the second memory cells coupled between the BLs and the WLs;
• control circuitry including a bitline (BL) voltage source to supply a bias to the BLs, a wordline (WL) voltage source to apply a bias to the WLs, and control circuitry to control the BL voltage source and the WL voltage source;
• and
• a memory controller including one or more processors coupled to the control circuitry to:
• in response to a determination of a set command to be implemented on first memory cells of the memory array, control an execution of a set pre-read operation on the first memory cells by causing application, by one of the BL voltage source or the WL voltage source, of a first demarcation voltage VDM0 across each of the first memory cells during a set pre-read time period;
• and
• in response to a determination of a reset command to implemented on second memory cells of the memory array, control an execution of a reset pre-read operation on the second memory cells by causing application, by the BL voltage source and the WL voltage source, of a second demarcation voltage VDM3 across each of the second memory cells during a reset pre-read time period, wherein the set pre-read time period and the reset pre-read time period do not overlap, any of the BL voltage source or the WL voltage source to supply a single voltage value at any given time.