G06F 2117/04
Clock gating
G06F2117/04 (Clock gating) appears on 200 US grants and 175 published applications in this corpus.
Search patents in G06F- Granted patents
- 200
- Published applications
- 175
- Assignees
- 75
- Inventors
- 434
- Latest grant
- 2 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1995 | 1 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 1 | 0 |
| 2000 | 1 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 1 |
| 2004 | 1 | 2 |
| 2005 | 0 | 2 |
| 2006 | 3 | 6 |
| 2007 | 1 | 3 |
| 2008 | 5 | 10 |
| 2009 | 5 | 7 |
| 2010 | 6 | 8 |
| 2011 | 13 | 3 |
| 2012 | 10 | 7 |
| 2013 | 7 | 8 |
| 2014 | 14 | 10 |
| 2015 | 13 | 20 |
| 2016 | 10 | 8 |
| 2017 | 12 | 5 |
| 2018 | 10 | 13 |
| 2019 | 18 | 10 |
| 2020 | 14 | 7 |
| 2021 | 16 | 5 |
| 2022 | 10 | 11 |
| 2023 | 9 | 6 |
| 2024 | 9 | 8 |
| 2025 | 7 | 9 |
| 2026 | 4 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Apparatuses and methods to facilitate a reduction in area and power consumption of circuits and systems via clock-gating and an identification of qualifiers2 Jun 2026US 12,645,250 B2NXP B. V.
- Constructing hierarchical clock gating architectures via rewriting21 Apr 2026US 12,608,070 B2Intel Corporation
- Physical security protection for integrated circuits13 Jan 2026US 12,524,580 B2Nordic Semiconductor ASA
- Clock domain crossing verification with setup assistance13 Jan 2026US 12,524,596 B2Siemens Industry Software Inc.
- Stimuli-independent clock gating determination9 Dec 2025US 12,493,729 B2Texas Instruments Incorporated
- Low noise fpga clock systems and methods21 May 2026US 2026/0141149 A1Lattice Semiconductor Corporation
- Systems, Methods, and Devices of Design-For-Test Circuitry30 Apr 2026US 2026/0118420 A1Arm Limited
- Clock gating cloning in design for test practice16 Apr 2026US 2026/0105226 A1QUALCOMM Incorporated
- Embedded power pickup ic device, layout, and method19 Mar 2026US 2026/0082704 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Clock gating and clock scaling based on runtime application task graph information12 Mar 2026US 2026/0072659 A1Altera Corporation
Most cited
By later US patents
- Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system311US 5,452,239 AQuickturn Design Systems, Inc. · 1995
- Array of parallel programmable processing engines and deterministic method of operating the same76US 7,401,333 B2TranSwitch Corporation · 2008
- Automatic synthesis of clock distribution networks67US 8,205,182 B1Cadence Design Systems, Inc. · 2012
- Method and apparatus for optimizing a gated clock structure using a standard optimization tool53US 5,980,092 AUnisys Corporation · 1999
- Identification and implementation of clock gating in the design of integrated circuits41US 7,076,748 B2Atrenta, Inc. · 2006