Physical security protection for integrated circuits

Abstract

An integrated circuit comprising a detection circuit portion for detecting an electromagnetic pulse attack on the integrated circuit is provided. The detection circuit portion comprises a shadow flip-flop comprising a clock input and a clock net connected to said clock input. The detection circuit portion also comprises a clock gate connected to the clock net that is controlled by an enable signal to selectively be in an open state in which the clock gate passes a clock signal to the clock net or in a closed state in which the clock gate does not pass the clock signal to the clock net. The detection circuit portion further comprises an error circuit portion, wherein the error circuit portion is arranged to selectively output an error signal if: the shadow flip-flop is clocked by a signal from the clock net and the clock gate is in the closed state.

Dependencies are inferred from the claim text.