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AssigneeUnisys Corporation
InventorsKenneth E. Merryman, Kevin C. Cleereman, Kenneth L. Engelbrecht
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A method and apparatus for using an optimization tool to optimize a design that uses a gated clock structure. In short, the present invention allows a standard optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate, wherein the logic gate forms a gated clock signal. Typically, standard optimizer tools can only check the relative timing between two or more signals that arrive at a storage element. In accordance with the present invention, selected logic gates may be modeled as a storage element. Thus, a standard optimizer tool may be used to correctly optimize a design that uses a gated clock structure, and in particular, to correctly optimize the logic that provides the clock and enable signals to a clock gating element.
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of:
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of:
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of:
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of:
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of:
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of:
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of:
Apparatus for,optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising:
Apparatus for optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising:
Apparatus for,optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising:
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:
Dependencies are inferred from the claim text.