Embedded power pickup ic device, layout, and method

A method of manufacturing an integrated circuit (IC) device, the method comprising:

• constructing first and second isolation structures and a plurality of stacked complementary field-effect transistors (CFETs) on a front side of a semiconductor substrate, the constructing the plurality of stacked CFETs comprising:
• forming pluralities of gates and metal-like defined (MD) segments extending in a first direction between the first and second isolation structures in a second direction perpendicular to the first direction;
• and
• forming an interconnect structure adjacent to and aligned with the plurality of gates in the first direction,
• wherein a portion of an MD segment of the plurality of MD segments is aligned with the interconnect structure in a third direction perpendicular to each of the first and second directions;
• forming a frontside via on one of the portion of the MD segment or the interconnect structure;
• forming a frontside conductive line on the frontside via and extending in the second direction;
• forming a backside via on the other of the MD segment or the interconnect structure;
• and
• forming a backside conductive line on the backside via and extending in the second direction.

A method of generating an integrated circuit (IC) layout diagram, the method comprising:

• extending an interconnect region across a width of a cell;
• overlapping the interconnect region with a metal-like defined (MD) region;
• overlapping the interconnect region and the MD region with a frontside via region and a backside via region;
• overlapping the frontside via region with a frontside metal region and the backside via region with a backside metal region, each of the frontside and backside metal regions extending in a cell width direction;
• and
• storing the IC layout diagram comprising the cell in a storage device.