Clock domain crossing verification with setup assistance

A system comprising:

• a memory device configured to store machine-readable instructions;
• and
• a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
• identify one or more violations associated with clock domain crossings in a circuit design based, at least in part, on static verification operations performed on the circuit design with a set of design constraints characterizing portions of an electronic device described by the circuit design;
• analyze the circuit design and the set of the design constraints by grouping clock signals in the circuit design into multiple asynchronous clock groups or by grouping the clock domain crossings in the circuit design based on a commonality of transmission registers for the clock domain crossings to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the set of the design constraints;
• and
• generate one or more additional design constraints to integrate into the set of the design constraints based on the asynchronous clock groups and the violations associated with the clock domain crossings in the circuit design or a presence of synchronizing circuitry utilized in the clock domain crossings for the groups and the violations associated with the clock domain crossings in the circuit design.

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• identifying, one or more violations associated with clock domain crossings in a circuit design based, at least in part, on static verification operations performed on the circuit design with a set of design constraints characterizing portions of an electronic device described by the circuit design;
• analyzing the circuit design and the set of the design constraints by grouping clock signals in the circuit design into multiple asynchronous clock groups or by grouping the clock domain crossings in the circuit design based on a commonality of transmission registers for the clock domain crossings to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the set of the design constraints;
• and
• generating one or more additional design constraints to integrate into the set of the design constraints based on the asynchronous clock groups and the violations associated with the clock domain crossings in the circuit design or a presence of synchronizing circuitry utilized in the clock domain crossings for the groups and the violations associated with the clock domain crossings in the circuit design.