Clock gating cloning in design for test practice
AssigneeQUALCOMM Incorporated
InventorsPaul POLICKE, Shwetha SHIVASHANKAR MURTHY
Life of this patent
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Abstract
A method of managing a clock signal in a design for test process for testing one or more processing cores includes applying a clock signal to a circuit to test one or more cores in accordance with a design for test process. The circuit includes at least a first clock gate path and a second clock gate path. One or more clock gates is controlled to disable at least one of the first clock gate path of the circuit or the second clock gate path based on a test mode of the design for test process.
Claims17
An apparatus for managing a clock in a design for test process for testing a processing core, the apparatus comprising:
- a first clock gate coupled to one or more internal registers on a first clock gate path;
- at least one clone of the first clock gate coupled to at least one wrapper chain on a second clock gate path;
- and
- a first user-defined clock gate coupled to the first clock gate, the first user-defined clock gate being configured to gate a clock signal to the one or more internal registers based on a mode of the design for test process.
A method comprising:
- applying a clock signal to a circuit to test one or more cores in accordance with a design for test process, the circuit including at least a first clock gate path and a second clock gate path;
- and
- controlling one or more clock gates to disable at least one of the first clock gate path of the circuit or the second clock gate path based on a test mode of the design for test process.
An apparatus comprising:
- means for applying a clock signal to a circuit to test one or more cores in accordance with a design for test process, the circuit including at least a first clock gate path and a second clock gate path;
- and
- means for controlling one or more clock gates to disable at least one of the first clock gate path of the circuit or the second clock gate path based on a test mode of the design for test process.
Dependencies are inferred from the claim text.