Apparatuses and methods to facilitate a reduction in area and power consumption of circuits and systems via clock-gating and an identification of qualifiers

A circuit comprising:

• a plurality of flip-flops;
• first logic that provides respective data at a first input of each flip-flop of the plurality of flip-flops, wherein the first logic does not obtain outputs of the flip-flops as inputs;
• and
• second logic that clock-gates a clock signal in respect of a second input of each of the plurality of flip-flops;
• wherein the first logic includes a plurality of multiplexers;
• wherein the second logic is driven from an output of a multiplexer;
• wherein a respective control input that provides for a selection amongst a respective plurality of inputs coupled to each of the plurality of multiplexers and a control input that provides for selection at the multiplexer are driven from a common signal.

A method, comprising:

• identifying, by a processing system including a processor, a plurality of qualifiers that impact data of an application, resulting in a first identification;
• identifying, by the processing system and based on the first identification, at least one clock-gating opportunity in respect of a circuit to implement the application, resulting in a second identification;
• and
• synthesizing, by the processing system and based on the second identification, the circuit, wherein the identifying of the plurality of qualifiers comprises generating a truth table, and wherein the identifying of the at least one clock-gating opportunity comprises analyzing the truth table.