Constructing hierarchical clock gating architectures via rewriting
AssigneeIntel Corporation
InventorsSamuel Coward, Theo Drane, George A. Constantinides, Emiliano Morini
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Abstract
Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.
Claims20
A method comprising:
- generating an equality graph (e-graph) for first register transfer level (RTL) code;
- expanding the e-graph by rewriting expressions in the e-graph using a variety of equivalence preserving transformations;
- detecting clock gating opportunities within the first RTL code based on the e-graph rewrites;
- generating second RTL code that includes hardware descriptions for clock gating circuitry for the clock gating opportunities detected within the first RTL;
- and
- generating updated first RTL code including the second RTL code.
A non-transitory machine-readable medium having instructions stored thereon, the instructions, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- generating an equality graph (e-graph) for first register transfer level (RTL) code;
- expanding the e-graph by rewriting expressions in the e-graph using a variety of equivalence preserving transformations;
- detecting clock gating opportunities within the first RTL code based on the e-graph rewrites;
- generating second RTL code that includes hardware descriptions for clock gating circuitry for the clock gating opportunities detected within the first RTL;
- and
- generating updated first RTL code including the second RTL code.
A data processing system comprising:
- a memory device configured to store instructions;
- and
- one or more processors configured to execute the instructions, wherein the instructions cause the one or more processors to:
- generate an equality graph (e-graph) for first register transfer level (RTL) code;
- expand the e-graph via a rewrite of expressions in the e-graph using a variety of equivalence preserving transformations;
- detect clock gating opportunities within the first RTL code based on the e-graph rewrites;
- generate second RTL code that includes hardware descriptions for clock gating circuitry for the clock gating opportunities detected within the first RTL;
- and
- generate updated first RTL code including the second RTL code.
Dependencies are inferred from the claim text.