Low noise fpga clock systems and methods
AssigneeLattice Semiconductor Corporation
InventorBradley A. Sharpe-Geisler
Life of this patent
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Abstract
Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). A method includes configuring a programmable logic device (PLD) having a fabric of programmable logic blocks arranged in a plurality of regions; routing data carry chains in a first direction across the fabric to each of the plurality of regions; placing global clock circuitry at a first edge of the PLD; and routing the global clock to a corresponding first edge of each region via a global clock trunk and a plurality of clock branches, the global clock trunk propagating the global clock signal across the fabric and in each region, in the same direction as the data carry chains.
Claims20
A method comprising:
- configuring a programmable logic device (PLD) comprising a fabric of programmable logic blocks arranged in a plurality of regions;
- routing data carry chains in a first direction across the fabric to each of the plurality of regions;
- placing global clock circuitry at a first edge of the PLD;
- and
- routing the global clock to a corresponding first edge of each region via a global clock trunk and a plurality of clock branches, the global clock trunk propagating the global clock signal in across the fabric and each region, in the same direction as the data carry chains.
A programmable logic device (PLD) comprising:
- a fabric of programmable logic blocks arranged in a plurality of regions;
- data carry chain routing configured to propagate in a first direction across the fabric to each of the plurality of regions;
- global clock circuitry located at a first edge of the PLD;
- and
- global clock routing comprising a global clock trunk and a plurality of global clock branches configured to propagate a global clock signal from the first edge of the PLD to a corresponding first edge of each region, wherein the global clock trunk propagates the global clock signal across the fabric and each region, in the same direction as the data carry chains.
Dependencies are inferred from the claim text.