G03F 9/7084
Position of mark on substrate, i.e. position in of mark
Official title: {Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels}
G03F9/7084 (Position of mark on substrate, i.e. position in of mark) appears on 650 US grants and 644 published applications in this corpus.
Search patents in G03F- Granted patents
- 650
- Published applications
- 644
- Assignees
- 198
- Inventors
- 1,289
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 2 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 3 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 2 | 0 |
| 1992 | 0 | 0 |
| 1993 | 3 | 0 |
| 1994 | 3 | 0 |
| 1995 | 3 | 0 |
| 1996 | 4 | 0 |
| 1997 | 4 | 0 |
| 1998 | 5 | 0 |
| 1999 | 10 | 0 |
| 2000 | 15 | 0 |
| 2001 | 17 | 13 |
| 2002 | 18 | 25 |
| 2003 | 26 | 24 |
| 2004 | 22 | 36 |
| 2005 | 28 | 42 |
| 2006 | 29 | 50 |
| 2007 | 38 | 44 |
| 2008 | 36 | 37 |
| 2009 | 32 | 35 |
| 2010 | 24 | 28 |
| 2011 | 27 | 32 |
| 2012 | 33 | 17 |
| 2013 | 24 | 22 |
| 2014 | 23 | 14 |
| 2015 | 19 | 21 |
| 2016 | 11 | 8 |
| 2017 | 16 | 15 |
| 2018 | 19 | 17 |
| 2019 | 20 | 34 |
| 2020 | 23 | 31 |
| 2021 | 26 | 18 |
| 2022 | 23 | 22 |
| 2023 | 20 | 17 |
| 2024 | 16 | 15 |
| 2025 | 15 | 15 |
| 2026 | 7 | 12 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Metrology method and apparatus8 Sep 2026US 12,730,388 B2ASML Netherlands B. V.
- Methods to process 3D semiconductor devices and structures which have metal layers16 Jun 2026US 12,660,326 B2Monolithic 3D Inc.
- Semiconductor structure with overlay mark, method of manufacturing the same, and system for manufacturing the same31 Mar 2026US 12,593,661 B2Nanya Technology Corporation
- Electronic devices comprising overlay marks24 Mar 2026US 12,588,515 B2Micron Technology, Inc.
- Overlay marks for reducing effect of bottom layer asymmetry17 Feb 2026US 12,554,206 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Alignment apparatus, lithography apparatus, and article manufacturing method17 Sep 2026US 2026/0277125 A1Canon Kabushiki Kaisha
- Semiconductor device having alignment mark27 Aug 2026US 2026/0251989 A1Micron Technology, Inc.
- Adjustment method, imprint method, article manufacturing method, and imprint apparatus13 Aug 2026US 2026/0233440 A1Canon Kabushiki Kaisha
- Methods and systems for determining reticle deformations16 Jul 2026US 2026/0202756 A1ASML Netherlands B. V.
- Maskless exposure system having image processing function for substrate positioning14 May 2026US 2026/0133503 A1SDA Co., Ltd.
Most cited
By later US patents
- On-axis interferometric alignment of plates using the spatial phase of interference patterns174US 5,414,514 AMassachusetts Institute of Technology · 1995
- Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same170US 6,288,454 B1LSI Logic Corporation · 2001
- Semiconductor integrated circuit device, and fabrication process and designing method thereof134US 6,261,883 B1Hitachi, Ltd. · 2001
- Device structures including backside contacts, and methods for forming same101US 7,816,231 B2International Business Machines Corporation · 2010
- Apparatus and methods for detecting overlay errors using scatterometry96US 7,242,477 B2KLA-Tencor Technologies Corporation · 2007