Semiconductor integrated circuit device, and fabrication process and designing method thereof

A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

• etching a semiconductor substrate to form a trench in regions defining active regions and dummy regions;
• depositing an insulating film over said active regions, dummy regions and trench;
• and
• polishing said insulating film to embed said trench with said insulating film;
• a distance between adjacent dummy and active regions being not greater than twice the depth of said trench, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions.

A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

• etching a semiconductor substrate to form a trench in regions defining active regions and dummy regions;
• depositing an insulating film on said active regions, dummy regions and trench;
• and
• polishing said insulating film to embed said trench with said insulating film;
• the width of said dummy regions being at least twice the minimum line width required by the resolution power of lithography, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions.

A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

• etching a silicon nitride film deposited on the principal surface of a semiconductor substrate and etching said semiconductor substrate to form a trench in regions defining active regions and dummy regions, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions;
• depositing an insulating film over said active and dummy regions and trench;
• polishing said insulating film using an alkaline slurry which contains a silicon oxide as an abrasive to embed said trench with said insulating film;
• and
• subsequent to said polishing step, etching said insulating film formed in said trench to make the height of the surface of said insulating film equal to or lower than the principal surface of said semiconductor substrate.

A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

• etching a silicon nitride film deposited on the principal surface of a semiconductor substrate and etching said semiconductor substrate to form a trench in regions defining active regions and dummy regions, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions;
• depositing an insulating film over said active and dummy regions and trench;
• and
• polishing said insulating film using cerium oxide as an abrasive to embed said trench with said insulating film.

A method of fabricating a semiconductor integrated circuit device, comprising the steps of:

• etching a semiconductor substrate to form a trench in a region defining active regions and dummy regions, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of the same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions;
• forming a first insulating film over said trench, active regions and dummy regions;
• polishing said first insulating film to embed said trench with said first insulating film;
• and
• forming gate interconnections and dummy interconnections by patterning a conductive film formed over said active regions, dummy regions and first insulating film, wherein said dummy interconnections are formed respectively between adjacent gate interconnections, wherein said dummy interconnections, formed between said adjacent gate interconnections, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy interconnections are located so as to be regularly repeated between si adjacent gate interconnections,
• wherein said gate interconnections serve as gate electrodes of MISFETs formed over said active regions, and
• wherein said dummy interconnections are formed over said first insulating film.

A method of fabricating a semiconductor integrated circuit device, comprising the steps of:

• forming in a semiconductor substrate an element isolation region defining active regions;
• forming gate interconnections and dummy interconnections by patterning a conductive film formed over said semiconductor substrate, wherein said dummy interconnections are formed respectively between adjacent gate interconnections, wherein said dummy interconnections, formed between said adjacent gate interconnections, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy interconnections are located so as to be regularly repeated between said adjacent gate interconnections;
• forming a first insulating film over said gate interconnections and dummy interconnections;
• and
• polishing said first insulating film,
• wherein said gate interconnections serve as gate electrodes of MISFETs formed over said active regions, and
• wherein said dummy interconnections are formed over said element isolation region.

A method of fabricating a semiconductor integrated circuit device including metal insulator semiconductor field effect elements, comprising the steps of:

• (a) providing a semiconductor substrate having a principal surface, said principal surface including active areas for said elements to be formed, and an isolation area for providing a required space between said active areas;
• (b) forming a trench pattern in said semiconductor substrate except for said active areas, thereby to form a plurality of dummy semiconductor regions, separated from each other by said trench pattern, at said isolation area,
• said trench pattern having a selected trench portion formed at a portion of said isolation area where a gate interconnection for said elements is to be provided, and having another trench portion formed so as to define active semiconductor regions at said active areas,
• said dummy semiconductor regions being of the same size in width and length as each other and being located so as to be regularly repeated at said isolation area;
• (c) depositing a first insulating film over said principal surface of the semiconductor substrate having said trench pattern;
• (d) removing said first insulating film from said principal surface to embed a resultant first insulating film in said trench pattern;
• (e) forming a first conductive film over gate insulating films, which are formed on said active semiconductor regions and said dummy semiconductor regions, and said resultant first insulating film embedded in said trench pattern;
• (f) patterning said first conductive film thereby to form gate electrodes over said gate insulating films covering said active semiconductor regions, and to form a gate interconnection over the selected portion of said trench pattern at said isolation area;
• (g) applying a flattened second insulating film over all areas of said active areas and said isolation area;
• and
• (h) forming interconnections extending on said second insulating film by patterning a second conductive film formed over said second insulating film.

A method of fabricating a semiconductor integrated circuit device including metal insulator semiconductor field effect elements, comprising the steps of:

• (a) providing a semiconductor substrate having a principal surface, said principal surface including active areas for said elements to be formed, and an isolation area for providing a required space between said active areas;
• (b) forming a trench pattern in said semiconductor substrate except for said active areas, thereby to form a plurality of dummy semiconductor regions, separated from each other by said trench pattern, at said isolation area,
• said trench pattern having a selected trench portion formed at a portion of said isolation area where a gate interconnection for said elements is to be provided, and having another trench portion formed so as to define active semiconductor regions at said active areas;
• said dummy semiconductor regions being of the same size in width and length as each other and being located so as to be regularly repeated at said isolation area;
• (c) depositing a first insulating film over said principal surface of the semiconductor substrate having said trench pattern;
• (d) removing said first insulating film from said principal surface to embed a resultant first insulating film in said trench pattern;
• (e) forming a first conductive film over gate insulating films, which are formed on said active semiconductor regions and said dummy semiconductor regions, and over said resultant first insulating film embedded in said trench pattern;
• (f) patterning said first conductive film thereby to form gate electrodes over said gate insulating films covering said active semiconductor regions, to form a gate interconnection over said selected portion of the trench pattern at said isolation area, and to form dummy interconnections over said gate insulating films covering said dummy semiconductor regions,
• said dummy interconnections being under an electrically floating state;
• (g) applying a flattened second insulating film over all areas of said active areas and said isolation area;
• and
• (h) forming interconnections extending on said second insulating film by patterning a second conductive film formed over said second insulating film.