G01R 31/31715
Testing of input or output circuits
Official title: {Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer}
G01R31/31715 (Testing of input or output circuits) appears on 464 US grants and 388 published applications in this corpus.
Search patents in G01R- Granted patents
- 464
- Published applications
- 388
- Assignees
- 164
- Inventors
- 690
- Latest grant
- 21 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 3 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 2 | 0 |
| 1994 | 7 | 0 |
| 1995 | 5 | 0 |
| 1996 | 2 | 0 |
| 1997 | 11 | 0 |
| 1998 | 8 | 0 |
| 1999 | 13 | 0 |
| 2000 | 8 | 0 |
| 2001 | 19 | 9 |
| 2002 | 15 | 18 |
| 2003 | 9 | 20 |
| 2004 | 27 | 35 |
| 2005 | 25 | 28 |
| 2006 | 18 | 23 |
| 2007 | 28 | 36 |
| 2008 | 34 | 22 |
| 2009 | 30 | 27 |
| 2010 | 37 | 25 |
| 2011 | 19 | 22 |
| 2012 | 17 | 8 |
| 2013 | 20 | 13 |
| 2014 | 6 | 9 |
| 2015 | 9 | 7 |
| 2016 | 7 | 3 |
| 2017 | 8 | 9 |
| 2018 | 7 | 10 |
| 2019 | 10 | 8 |
| 2020 | 9 | 10 |
| 2021 | 7 | 6 |
| 2022 | 10 | 12 |
| 2023 | 7 | 9 |
| 2024 | 14 | 7 |
| 2025 | 6 | 6 |
| 2026 | 1 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis21 Jul 2026US 12,687,578 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Self-test for receive and transmit hardware functional safety associated with a touch panel or screen16 Dec 2025US 12,498,418 B1Cypress Semiconductor Corporation
- Temporal lockstep4 Nov 2025US 12,461,145 B1Alma Mater Studiorum - Università di Bologna
- Can transceiver and method for the can transceiver28 Oct 2025US 12,455,314 B2NXP B. V.
- Secured scan access for a device including a scan chain13 May 2025US 12,298,346 B2Texas Instruments Incorporated
- Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis8 Oct 2026US 2026/0309778 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Cross-die high-speed access and test implementation for in-package chiplet23 Jul 2026US 2026/0211033 A1Cisco Technology, Inc.
- Esd (electrostatic discharge) verification for large io (input/output) arrays25 Jun 2026US 2026/0177611 A1Intel Corporation
- Probe device and test device including the same23 Apr 2026US 2026/0110732 A1Samsung Electronics Co., Ltd.
- Level Shifter Circuit19 Mar 2026US 2026/0079204 A1NXP B. V.
Most cited
By later US patents
- IC card with dual level power supply interface and method for operating the IC card202US 5,490,117 ASeiko Epson Corporation · 1996
- Efficient fir filter for high-speed communication118US 6,272,173 B1Broadcom Corporation · 2001
- Wafer scale testing of redundant integrated circuit dies101US 4,956,602 AAmber Engineering, Inc. · 1990
- Semiconductor device for reducing the number of probing pad used during wafer test and method for testing the same98US 7,002,364 B2Hynix Semiconductor Inc. · 2006
- Pair-swap independent trellis decoder for a multi-pair gigabit transceiver95US 6,865,234 B1Broadcom Corporation · 2005