Temporal lockstep

A system comprising:

• an instruction memory;
• a processor core comprising a pipeline including an instruction fetch circuit and an instruction decode and execute circuit;
• wherein the instruction decode and execute circuit comprises a controller including a finite state machine, wherein the finite state machine comprises a plurality of states to control the processor core;
• a voting circuit configured to provide a control signal to control the finite state machine for transitioning from a current state of the plurality of states to a next state;
• wherein the processor core, based at least on the plurality of states of the finite state machine, is configured to:
• fetch a first instruction from the instruction memory;
• generate a first dummy instruction based on the first instruction and a first real instruction based on the first instruction;
• execute the first dummy instruction to generate a first dummy result;
• store the first dummy result in a first dummy buffer;
• execute the first real instruction to generate a first real result;
• and
• compare the first dummy result stored in the first dummy buffer with the first real result to identify an error.

A method comprising:

• providing a processor core comprising a pipeline including an instruction fetch circuit and an instruction decode and execute circuit;
• wherein the instruction decode and execute circuit comprises a controller including a finite state machine, wherein the finite state machine comprises a plurality of states to control the processor core;
• providing a voting circuit configured to provide a control signal to control the finite state machine for transitioning from a current state of the plurality of states to a next state;
• fetching, with the instruction fetch circuit, a first instruction;
• generating a first dummy instruction based on the first instruction and a first real instruction based on the first instruction;
• executing, with the instruction decode and execute circuit, a first dummy instruction to generate a first dummy result;
• store the first dummy result in a first dummy buffer;
• executing, with the instruction decode and execute circuit, the first real instruction to generate a first real result;
• and
• comparing the first dummy result stored in the first dummy buffer with the first real result to identify an error.