Level Shifter Circuit

A level shifter test circuit comprising:

• a first level shifter for translating a signal from a first domain to a second domain, the first level shifter configured to:
• receive the signal as an input from the first domain;
• and
• output a translated signal which has been translated by the first level shifter for the second domain, wherein the translated signal is split between a first output signal and a first level shifter feedback signal;
• and
• test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.

A method of testing a level shifter circuit, the method comprising:

• providing a first input signal to a first level shifter and translating the first input signal from a first domain to a second domain, wherein an output translated signal from the first level shifter is split between a first output signal of the second domain and a first level shifter feedback signal for testing operation of the first level shifter;
• receiving the first level shifter feedback signal at a first test logic;
• and
• determining whether the level shifter circuit is working or not based on the output of the test logic.

A semiconductor chip comprising a level shifter test circuit comprising:

• a first level shifter for translating a signal from a first domain to a second domain, the first level shifter configured to:
• receive the signal as an input from the first domain;
• and
• output a translated signal which has been translated by the first level shifter for the second domain, wherein the translated signal is split between a first output signal and a first level shifter feedback signal;
• and
• test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.